FinFET 6T SRAM cell structure

1. A static memory circuit comprising:

a pull-up (PU) transistor comprising a number of Fins;

a pull-down (PD) transistor comprising a number of Fins;

a pass-gate (PG) transistor associated with the PU transistor and the PD transistor; and

first and second word lines electrically insulated from each other, wherein:

the PG transistor comprises a number of Fins, and a gate electrode comprising a number of first gates and a number of second gates each disposed on one of the Fins of the PG transistor, the first gates being connected to the first word line, and the second gates being connected to the second word line;

during a read operation, one of the first and second word lines is asserted low, so that a ratio of the number of Fins of the PD transistor and the number of Fins of the PG transistor is greater than or equal to a first predetermined value; and

during a write operation, one of the first and second word lines is asserted high, so that a ratio of the number of Fins of the PG transistor and the number of Fins of the PU transistor is greater than or equal to a second predetermined value.

2. The static memory circuit of claim 1 , wherein a ratio of the number of Fins of the PU transistor, the number of Fins of the PD transistor, and the number of Fins of the PG transistor is 1:2:2.

3. The static memory circuit of claim 2 , wherein the number of Fins of the PU transistor is 1, the number of Fins of the PD transistor is 2, the number of Fins of the PG transistor is 2, the number of first gates is 1, and the number of second gates is 1; or

the number of Fins of the PU transistor is 2, the number of Fins of the PD transistor is 4, the number of Fins of the PG transistor is 4, the number of first gates is 1, and the number of second gates is 3; or the number of first gates is 2, and the number of second gates is 2; or

the number of Fins of the PU transistor is 3, the number of Fins of the PD transistor is 6, the number of Fins of the PG transistor is 6, the number of first gates is 1, and the number of second gates is 5; or, the number of first gates is 2, and the number of second gates is 4; or, the number of first gates is 3, and the number of second gates is 3.

4. The static memory circuit of claim 1 , wherein a ratio of the number of Fins of the PU transistor, the number of Fins of the PD transistor, and the number of Fins of the PG transistor is 1:3:3.

5. The static memory circuit of claim 4 , wherein the number of Fins of the PU transistor is 1, the number of Fins of the PD transistor is 3, the number of Fins of the PG transistor is 3, the number of first gates is 1, and the number of second gates is 2; or

the number of Fins of the PU transistor is 2, the number of Fins of the PD transistor is 6, the number of Fins of the PG transistor is 6, the number of first gates is 1, and the number of second gates is 5; or, the number of first gates is 2, and the number of second gates is 4; or, the number of first gates is 3, and the number of second gates is 3; or

the number of Fins of the PU transistor is 3, the number of Fins of the PD transistor is 9, the number of Fins of the PG transistor is 9, the number of first gates is 1, and the number of second gates is 8; or, the number of first gates is 2, and the number of second gates is 7; or, the number of first gates is 3, and the number of second gates is 6, or, the number of first gates is 4, and the number of second gates is 5.

6. The static memory circuit of claim 1 , wherein the first predetermined value is 1.2 and the second predetermined value is 1.5.

7. The static memory circuit of claim 1 , wherein the PU transistor is a PMOS transistor, and each of the PD and PG transistors is an NMOS transistor.

8. A static memory circuit comprising:

a number of word lines;

a bit line; and

first and second units, each of the first and second units comprising:

a pull-up (PU) transistor comprising a number of Fins;

a pull-down (PD) transistor comprising a number of Fins;

a pass-gate (PG) transistor comprising:

a number of Fins;

a gate electrode connected to the word line;

a source or a drain connected to the bit line; wherein

a ratio of the number of Fins of the PD transistor and the number of Fins of the PG transistor is greater than or equal to a first predetermined value; and

a ratio of the number of Fins of the PG transistor and the number of Fins of the PU transistor is greater than or equal to a second predetermined value.

9. The static memory circuit of claim 8 , wherein the number of word lines is 1, a ratio of the number of Fins of the PU transistor, the number of Fins of the PD transistor, and the number of Fins of the PG transistor is 1:4:2.

10. The static memory circuit of claim 8 , wherein the number of word lines is 2 including a first word line and a second word line electrically insulated from each other; the gate electrode comprises a number of first gates and a number of second gates each disposed on one of the Fins of the PG transistor, the first gates being connected to the first word line, and the second gates being connected to the second word line; wherein one of the first and second word lines is asserted low during a read operation, and asserted high during a write operation.

11. The static memory circuit of claim 8 , wherein:

the number of Fins of the PU transistor in the first unit is equal to the number of Fins of the PU transistor in the second unit;

the number of Fins of the PD transistor in the first unit is equal to the number of Fins of the PD transistor in the second unit; and

the number of Fins of the PG transistor in the first unit is equal to the number of Fins of the PG transistor in the second unit.

12. The static memory circuit of claim 8 , wherein:

the number of Fins of the PU transistor in the first unit is not equal to the number of Fins of the PU transistor in the second unit; or

the number of Fins of the PD transistor in the first unit is not equal to the number of Fins of the PD transistor in the second unit; or

the number of Fins of the PG transistor in the first unit is not equal to the number of Fins of the PG transistor in the second unit.

13. A semiconductor device comprising:

a substrate; and

a static memory circuit comprising:

a number of word lines;

a bit line; and

first and second units, each of the first and second units comprising:

a pull-up (PU) transistor comprising a number of Fins;

a pull-down (PD) transistor comprising a number of Fins;

a pass-gate (PG) transistor comprising a number of Fins, a gate electrode connected to the word lines, and a source or a drain connected to the bit line;

wherein:

a ratio of the number of Fins of the PD transistor and the number of Fins of the PG transistor is greater than or equal to a first predetermined value; and

a ratio of the number of Fins of the PG transistor and the number of Fins of the PU transistor is greater than or equal to a second predetermined value.

14. The semiconductor device of claim 13 , wherein the substrate comprises a first active region, a second active region, a third active region, and a fourth active region, wherein:

in the first unit, the PU transistor is disposed in the second active region, and the PD transistor and the PG transistor are disposed in the first active region; and

in the second unit, the PU transistor is disposed in the third active region, and the PD transistor and the PG transistor are disposed in the fourth active region.

15. The semiconductor device of claim 14 , wherein the first active region is a p-well region, the second active region is an n-well region, the third active region is an n-well region, and the fourth active region is a p-well region.