Single diffusion break
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor, a second transistor, and a third transistor separated by their respective source/drain regions; and a diffusion break between the second transistor and the third transistor, wherein a first distance between a center of a gate of the first transistor and a center of a gate of the second transistor is more than half of a second distance between the center of the gate of the second transistor and a center of a gate of the third transistor. A method of manufacturing the semiconductor structure is also provided.
1 . A semiconductor structure comprising:
a first transistor, a second transistor, and a third transistor separated by their respective source/drain regions; and
a diffusion break between the second transistor and the third transistor,
wherein the second transistor has a first source/drain region shared with the first transistor, and has a second source/drain region at a first side of the diffusion break and in direct contact with the diffusion break; and wherein the third transistor has a first source/drain region at a second side of the diffusion break and in direct contact with the diffusion break, the second side being opposite the first side;
wherein a first distance between a center of a gate of the first transistor and a center of a gate of the second transistor is more than half of a second distance between the center of the gate of the second transistor and a center of a gate of the third transistor.
2 . The semiconductor structure of claim 1 , wherein the diffusion break has a width and the gates of the first, second, and third transistors have a length, wherein the width of the diffusion break is smaller than the length of the gates.
3 . The semiconductor structure of claim 2 , wherein the first, second, and third transistors have their respective sidewall spacers, wherein two opposing sidewall spacers of the first transistor and the second transistor has a first gap and two opposing sidewall spacers of the second transistor and the third transistor has a second gap, and wherein the second gap equals two times the first gap plus the width of the diffusion break.
4 . The semiconductor structure of claim 1 , wherein the diffusion break is adjacent to a source/drain (S/D) epi region of the second transistor and adjacent to a S/D epi region of the third transistor.
5 . The semiconductor structure of claim 4 , wherein the diffusion break extends into a substrate underneath the second and third transistors to separate the S/D epi region of the second transistor from the S/D epi region of the third transistor.
6 . The semiconductor structure of claim 1 , further comprising a fourth transistor next to the third transistor, wherein a third distance between the center of the gate of the third transistor and a center of a gate of the fourth transistor equals to the first distance.
7 . A semiconductor structure comprising:
a first transistor, a second transistor, a third transistor, and a fourth transistor separated by their respective source/drain regions, a first distance between the first and second transistors is more than half of a second distance between the second and third transistors; and
a diffusion break between the second transistor and the third transistor,
wherein the second transistor has a first source/drain region shared with the first transistor, and has a second source/drain region at a first side of the diffusion break and in direct contact with the diffusion break; the third transistor has a first source/drain region at a second side of the diffusion break and in direct contact with the diffusion break, and has a second source/drain region shared with the fourth transistor, the first side being opposite the second side.
8 . The semiconductor structure of claim 7 , wherein a center of a gate of the first transistor and a center of a gate of the second transistor has a first distance, and the center of the gate of the second transistor and a center of a gate of the third transistor has a second distance, wherein the second distance is less than two times the first distance.
9 . The semiconductor structure of claim 7 , wherein the diffusion break has a width and the gates of the first, second, third, and fourth transistors have a length, wherein the width of the diffusion break is smaller than the length of the gates.
10 . The semiconductor structure of claim 7 , wherein the first, second, third, and fourth transistors have their respective sidewall spacers, wherein two opposing sidewall spacers of the first transistor and the second transistor has a first gap and two opposing sidewall spacers of the second transistor and the third transistor has a second gap, wherein the second gap equals two times the first gap plus the width of the diffusion break.
11 . The semiconductor structure of claim 10 , wherein a third gap between two opposing sidewall spacers of the third transistor and the fourth transistor equals the first gap.
12 . The semiconductor structure of claim 7 , wherein the diffusion break is adjacent to a source/drain (S/D) epi region of the second transistor and adjacent to a S/D epi region of the third transistor.
13 . The semiconductor structure of claim 12 , wherein the diffusion break extends into a substrate underneath the second and third transistors to separate the S/D epi region of the second transistor from the S/D epi region of the third transistor.
14 . The semiconductor structure of claim 7 , wherein the diffusion break is a single diffusion break of dielectric material, and the first, second, third, and fourth transistors are nanosheet transistors.