IP Library › Granted Patent US 11,056,399
Granted Patent B2
US 11,056,399 · App. 16/380,487 · Granted Jul 6, 2021

Source and drain EPI protective spacer during single diffusion break formation

Inventors: Yao Yao (Albany, NY); Andrew M. Greene (Slingerlands, NY); Veeraraghavan S. Basker (Schenectady, NY); Kangguo Cheng (Schenectady, NY); Zhenxing Bi (Niskayuna, NY); Ruilong Xie (Niskayuna, NY)
Assignee: International Business Machines Corporation
H01L21/823481H01L21/823418H01L21/823431H01L27/0886H01L29/0649H01L29/66545H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 11,056,399
App. No.
16/380,487
Granted
Jul 6, 2021
Kind
B2
Abstract

A method is presented for forming single diffusion break (SDB) without damaging source and drain epitaxial growth regions. The method includes forming the source and drain epitaxial regions between sacrificial gates, the sacrificial gates formed over a plurality of fins, depositing an interlayer dielectric (ILD) over the source and drain epitaxial regions, performing SDB patterning, and removing at least one of the sacrificial gates to expose the plurality of fins. The method further includes recessing the plurality of fins to create a first opening, forming inner spacers within the opening, removing the plurality of fins to create a second opening, dimensions of the second opening defined by the inner spacers, and laterally etching the second opening to increase SDB width.

Claims (40)

1. A method for forming single diffusion break (SDB) without damaging source and drain epitaxial growth regions, the method comprising:

forming the source and drain epitaxial growth regions between sacrificial gates, the sacrificial gates formed over a plurality of fins, wherein a top surface of the source and drain epitaxial growth regions extends above a bottom surface of the sacrificial gates;

depositing an interlayer dielectric (ILD) over the source and drain epitaxial growth regions;

performing SDB patterning;

removing at least one of the sacrificial gates to expose the plurality of fins such that top surfaces of shallow trench isolation (STI) regions are exposed, the STI regions formed between the plurality of fins;

recessing the plurality of fins in a first etch process to create a first opening, the recessing resulting in remaining fin portions, and the first etch process completed once the top surfaces of the STI regions are reached;

forming inner spacers within the first opening;

removing the remaining fin portions in a second etch process to create a second opening, dimensions of the second opening defined by the inner spacers, the second etch process completed once bottom surfaces of the STI regions are reached; and

laterally etching the second opening in a third etch process to increase SDB width.

2. The method of claim 1 , wherein the SDB patterning involves employing an organic planarization layer (OPL) and an anti-reflective coating (ARC) layer.

3. The method of claim 1 , wherein the inner spacers are constructed from at least one of the following: SiC, SiOC, SiOCN, SiCO, SiO 2 .

4. The method of claim 1 , wherein the lateral etch is an isotropic etch.

5. The method of claim 1 , further comprising performing a dielectric fill in the SDB.

6. The method of claim 5 , wherein the dielectric fill directly contacts the inner spacers.

7. The method of claim 5 , wherein the dielectric fill creates an air gap in a region defined by the second opening.

8. The method of claim 1 , wherein creation of the first opening defines substrate portions that protect the source and drain epitaxial growth regions.

9. The method of claim 8 , wherein the inner spacers directly contact the substrate portions.

10. A method for forming single diffusion break (SDB) without damaging source and drain epitaxial growth regions, the method comprising:

forming the source and drain epitaxial growth regions between sacrificial gates, the sacrificial gates formed over a plurality of fins, wherein a top surface of the source and drain epitaxial growth regions extends above a bottom surface of the sacrificial gates;

performing SDB patterning;

removing at least one of the sacrificial gates to expose the plurality of fins such that top surfaces of shallow trench isolation (STI) regions are exposed, the STI regions formed between the plurality of fins;

anisotropically etching the plurality of fins to create a first opening in a first etch process, the anisotropic etching resulting in remaining fin portions, and the first etch process completed once the top surfaces of the STI regions are reached;

forming inner spacers within the first opening;

removing the remaining fin portions to create a second opening in a second etch process, the second etch process completed once bottom surfaces of the STI regions are reached; and

isotropically etching the second opening in a third etch process in a lateral direction with respect to the source and drain epitaxial growth regions to increase SDB width.

11. The method of claim 10 , further comprising depositing an interlayer dielectric (ILD) over the source and drain epitaxial growth regions before SDB patterning.

12. The method of claim 10 , further comprising performing a dielectric fill in the SDB.

13. The method of claim 12 , wherein the dielectric fill directly contacts the inner spacers.

14. The method of claim 12 , wherein the dielectric fill creates an air gap in a region defined by the second opening.

15. The method of claim 10 , wherein the SDB patterning involves employing an organic planarization layer (OPL) and an anti-reflective coating (ARC) layer.

16. The method of claim 10 , wherein the inner spacers are constructed from at least one of the following: SiC, SiOC, SiOCN, SiCO, SiO 2 .

17. The method of claim 10 , wherein creation of the first opening defines substrate portions that protect the source and drain epitaxial growth regions.

18. A semiconductor structure for forming single diffusion break (SDB) without damaging source and drain epitaxial growth regions, the semiconductor structure comprising:

the source and drain epitaxial growth regions disposed in direct contact with a substrate, wherein a top surface of the source and drain epitaxial growth regions extends above a bottom surface of sacrificial gates;

a conductive material disposed over the source and drain epitaxial regions;

inner spacers disposed between source and drain epitaxial regions;

a dielectric material disposed between the inner spacers and disposed between STI regions, the STI regions disposed between the substrate and the inner spacers, and at least one of the STI regions directly contacting a bottom surface of the inner spacers; and

an air gap defined within a distal end of the dielectric material.

19. The semiconductor structure of claim 18 , wherein the inner spacers are separated from the air gap by the dielectric material.

20. The semiconductor structure of claim 18 , wherein the inner spacers protect the source and drain epitaxial growth regions during SDB formation.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 10, 2019
From: YAO, YAO; GREENE, ANDREW M.; BASKER, VEERARAGHAVAN S.; CHENG, KANGGUO; BI, ZHENXING; XIE, RUILONG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 048849/0440 →
Continuity (1)
Related Publication 20200328121A1 · Oct 15, 2020
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