Semiconductor device
A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode extending in a second direction and crossing the active pattern, a gate capping pattern covering a top surface of the gate electrode, and a separation structure at a side of the gate electrode and extending in the second direction to penetrate the active pattern in a third direction. The first and second directions are parallel to a bottom surface of the substrate and are perpendicular to the third direction. The separation structure may include a filling pattern, which extends in the third direction to penetrate the active pattern, and a vertical insulating pattern, which is interposed between the filling pattern and the gate electrode. A top surface of the separation structure may be located at a height lower than a top surface of the gate capping pattern.
1. A semiconductor device, comprising:
a substrate comprising an active pattern extending in a first direction that is parallel to a bottom surface of the substrate;
a gate electrode extending in a second direction to cross the active pattern, the second direction parallel to the bottom surface of the substrate and crossing the first direction;
a gate capping pattern covering a top surface of the gate electrode; and
a separation structure at a side of the gate electrode and extending in the second direction to penetrate the active pattern in a third direction perpendicular to the bottom surface of the substrate,
wherein the separation structure comprises a filling pattern extending in the third direction to penetrate the active pattern, and a vertical insulating pattern interposed between the filling pattern and the gate electrode,
a top surface of the separation structure at a height lower than a top surface of the gate capping pattern with respect to a top surface of the substrate,
a middle portion of the separation structure has a bulge having a width in the first direction greater than a width at a top portion of the separation structure, and
the bulge is at a level below a top surface of the active pattern.
2. The semiconductor device of claim 1 , further comprising:
a separation capping pattern covering the top surface of the separation structure,
wherein a first width of the top surface of the separation structure in the first direction is less than a second width of a bottom surface of the separation capping pattern in the first direction.
3. The semiconductor device of claim 2 , wherein at least one of the filling pattern and the vertical insulating pattern comprises the same materials as the separation capping pattern.
4. The semiconductor device of claim 1 , wherein the filling pattern and the vertical insulating pattern comprise different materials from each other.
5. The semiconductor device of claim 4 , wherein the vertical insulating pattern comprises a material whose dielectric constant is less than that of the filling pattern.
6. The semiconductor device of claim 1 , wherein a top surface of the filling pattern and a top surface of the vertical insulating pattern is at a height lower than the top surface of the gate capping pattern with respect to the top surface of the substrate.
7. The semiconductor device of claim 1 , further comprising:
a separation spacer on a side surface of the separation structure,
wherein the vertical insulating pattern is interposed between the filling pattern and the separation spacer.
8. The semiconductor device of claim 7 , wherein a top surface of the separation spacer is located at a height lower than the top surface of the gate capping pattern.
9. The semiconductor device of claim 7 , further comprising:
a vertical pattern on the side surface of the separation structure,
wherein the vertical pattern is interposed between the vertical insulating pattern and the separation spacer.
10. The semiconductor device of claim 1 , wherein the gate capping pattern comprises a material having a polishing selectivity with respect to the separation structure.
11. The semiconductor device of claim 1 , wherein at least one of the filling pattern and the vertical insulating pattern comprises a material having a dielectric constant lower than that of the gate capping pattern.
12. The semiconductor device of claim 1 , wherein the separation structure comprises at least one of silicon carbon oxide or silicon oxide.
13. The semiconductor device of claim 1 , wherein a side surface of the separation structure has a profile protruding in the first direction at a level lower than a top surface of the active pattern.
14. A semiconductor device, comprising:
a substrate comprising an active pattern extending in a first direction parallel to a bottom surface of the substrate;
a gate electrode extending in a second direction to cross the active pattern, the second direction parallel to the bottom surface of the substrate and crossing the first direction;
a gate capping pattern covering a top surface of the gate electrode; and
a separation structure at a side of the gate electrode and extending in the second direction to penetrate the active pattern in a third direction perpendicular to the bottom surface of the substrate,
wherein the gate capping pattern comprises a material having a polishing selectivity with respect to the separation structure,
a middle portion of the separation structure has a bulge having a width in the first direction greater than a width at a top portion of the separation structure, and
the bulge is at a level below a top surface of the active pattern.
15. The semiconductor device of claim 14 , further comprising:
a separation capping pattern covering a top surface of the separation structure,
wherein a first width of the top surface of the separation structure in the first direction is less than a second width of a bottom surface of the separation capping pattern in the first direction.
16. The semiconductor device of claim 14 , wherein the separation structure comprises a filling pattern penetrating the active pattern in the third direction, and a vertical insulating pattern interposed between the filling pattern and the gate electrode.
17. The semiconductor device of claim 16 , wherein at least one of the filling pattern and the vertical insulating pattern comprises a material having a dielectric constant lower than that of the gate capping pattern.
18. The semiconductor device of claim 16 , wherein the gate capping pattern comprises a material having a polishing selectivity with respect to at least one of the filling pattern and the vertical insulating pattern.
19. A semiconductor device, comprising:
a substrate comprising an active pattern extending in a first direction parallel to a bottom surface of the substrate;
a gate electrode extending in a second direction to cross the active pattern, the second direction parallel to the bottom surface of the substrate and crossing the first direction;
a gate capping pattern covering a top surface of the gate electrode;
a separation structure at a side of the gate electrode and extending in the second direction to penetrate the active pattern in a third direction perpendicular to the bottom surface of the substrate; and
a separation capping pattern covering a top surface of the separation structure,
wherein a first width of the top surface of the separation structure in the first direction is less than a second width of a bottom surface of the separation capping pattern in the first direction,
a middle portion of the separation structure has a bulge having a width in the first direction greater than a width at a top portion of the separation structure, and
the bulge is at a level below a top surface of the active pattern.
20. The semiconductor device of claim 19 , wherein the separation structure comprises the same materials as the separation capping pattern.