Common-mode current removal schemes for digital-to-analog converters
Methods and apparatus for common-mode current removal in a digital-to-analog converter (DAC). An example DAC circuit generally includes a plurality of current-steering cells, a resistor ladder circuit coupled to the plurality of current-steering cells and having a plurality of shunt branches, and an adjustable resistance circuit coupled between middle nodes of the plurality of shunt branches and a reference potential node for the DAC circuit.
1. A digital-to-analog converter (DAC) circuit comprising:
a plurality of current-steering cells;
a resistor ladder circuit coupled to the plurality of current-steering cells and having a plurality of shunt branches; and
an adjustable resistance circuit coupled between middle nodes of the plurality of shunt branches and a reference potential node for the DAC circuit, wherein the adjustable resistance circuit comprises a switched network of resistive elements.
2. The DAC circuit of claim 1 , wherein the switched network of resistive elements comprises a binary-weighted network of resistive elements.
3. The DAC circuit of claim 2 , wherein the binary-weighted network of resistive elements comprises a network branch configured to selectively short the middle nodes of the plurality of shunt branches to the reference potential node.
4. The DAC circuit of claim 1 , wherein the switched network of resistive elements comprises a plurality of network branches coupled in parallel and wherein one or more of the network branches each comprise a switch coupled in series with a resistive element.
5. The DAC circuit of claim 4 , wherein another one of the plurality of network branches is configured to selectively short the switched network of resistive elements.
6. The DAC circuit of claim 4 , wherein another one of the plurality of network branches is configured to present a fixed resistance for the switched network of resistive elements when other switches in the switched network of resistive elements are open.
7. The DAC circuit of claim 4 , wherein one or more other network branches each comprise a plurality of resistive elements selectively coupled in series.
8. The DAC circuit of claim 1 , wherein the middle nodes of the plurality of shunt branches are shorted together.
9. The DAC circuit of claim 1 , wherein the adjustable resistance circuit is coupled to a first set of the middle nodes of the plurality of shunt branches.
10. The DAC circuit of claim 9 , further comprising one or more switches, each switch being coupled between one of a second set of the middle nodes of the plurality of shunt branches and the reference potential node for the DAC circuit, wherein the first set and the second set are disjoint sets.
11. A digital-to-analog converter (DAC) circuit comprising:
a plurality of current-steering cells;
a resistor ladder circuit coupled to the plurality of current-steering cells and having a plurality of shunt branches; and
a plurality of switches, each switch being coupled between a middle node of one of the plurality of shunt branches and a reference potential node for the DAC circuit.
12. The DAC circuit of claim 11 , wherein at least a portion of the plurality of switches are configured to be independently controlled.
13. The DAC circuit of claim 11 , wherein a number of the plurality of switches equals a number of the plurality of shunt branches and wherein a number of the plurality of current-steering cells equals the number of the plurality of shunt branches.
14. The DAC circuit of claim 11 , wherein the reference potential node comprises electrical ground.
15. A method of operating a digital-to-analog converter (DAC) circuit comprising a plurality of current-steering cells and a resistor ladder circuit coupled to the plurality of current-steering cells and having a plurality of shunt branches, the method comprising controlling an adjustable resistance circuit coupled between middle nodes of the plurality of shunt branches and a reference potential node for the DAC circuit, to sink at least a portion of a common-mode current of the DAC circuit from the shunt branches of the resistor ladder circuit, wherein the adjustable resistance circuit comprises a switched network of resistive elements.
16. The method of claim 15 , wherein the switched network of resistive elements comprises a binary-weighted network of resistive elements.
17. The method of claim 16 , further comprising controlling a switch in a network branch of the binary-weighted network of resistive elements to selectively short the middle nodes of the plurality of shunt branches to the reference potential node.
18. The method of claim 15 , wherein the switched network of resistive elements comprises a plurality of network branches coupled in parallel, wherein one or more of the network branches each comprise a switch coupled in series with a resistive element, and wherein controlling the adjustable resistance circuit comprises selectively closing the switch in each of the one or more of the network branches.
19. The method of claim 18 , further comprising controlling another switch in another one of the plurality of network branches to selectively short the switched network of resistive elements.
20. The method of claim 18 , wherein one or more other network branches each comprise a plurality of resistive elements selectively coupled in series and wherein controlling the adjustable resistance circuit further comprises controlling an effective number of the plurality of resistive elements coupled in series in each of the one or more other network branches.
21. The method of claim 15 , wherein the middle nodes of the plurality of shunt branches are shorted together.
22. The method of claim 15 , wherein the adjustable resistance circuit is coupled to a first set of the middle nodes of the plurality of shunt branches.
23. The method of claim 22 , further comprising controlling one or more switches, each switch being coupled between one of a second set of the middle nodes of the plurality of shunt branches and the reference potential node for the DAC circuit, wherein the first set and the second set are disjoint sets.
24. A method of operating a digital-to-analog converter (DAC) circuit comprising a plurality of current-steering cells and a resistor ladder circuit coupled to the plurality of current-steering cells and having a plurality of shunt branches, the method comprising controlling a plurality of switches, each switch being coupled between a middle node of one of the plurality of shunt branches and a reference potential node for the DAC circuit, to selectively sink portions of a common-mode current of the DAC circuit from the shunt branches of the resistor ladder circuit.
25. The method of claim 24 , wherein the controlling comprises independently controlling at least a portion of the plurality of switches.
26. The method of claim 24 , wherein a number of the plurality of switches equals a number of the plurality of shunt branches and wherein a number of the plurality of current-steering cells equals the number of the plurality of shunt branches in the resistor ladder circuit.