IP Library Granted Patent US 11,888,083
Granted Patent B2
US 11,888,083 · App. 17/811,761 · Granted Jan 30, 2024

Method for producing an optoelectronic semiconductor chip and optoelectronic semiconductor chip

Inventors: Werner Bergbauer (Windberg, DE); Thomas Lehnhardt (Regensburg, DE); Jürgen Off (Regensburg, DE); Joachim Hertkorn (Woerth an der Donau, DE)
Assignee: OSRAM Opto Semiconductors GmbH
H01L31/1852H01L21/0243H01L21/0254H01L21/02458H01L21/02639H01L21/02647H01L31/03044H01L31/1856H01L33/007H01L33/0066H01L33/0075H01L33/12H01L33/22H01L33/32H01L21/02488H01L2933/0033
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Quick Facts
Patent No.
US 11,888,083
App. No.
17/811,761
Granted
Jan 30, 2024
Kind
B2
Abstract

In an embodiment an electronic semiconductor chip includes a growth substrate with a growth surface including a flat region having a plurality of three-dimensionally designed surface structures on the flat region, a nucleation layer composed of oxygen-containing AlN in direct contact with the growth surface at the flat region and the three-dimensionally designed surface structures and a nitride-based semiconductor layer sequence on the nucleation layer, wherein the semiconductor layer sequence overlays the three-dimensionally designed surface structures, and wherein the oxygen content in the nucleation layer is greater than 10 19 cm −3 .

Claims (28)

1. An electronic semiconductor chip comprising:

a growth substrate with a growth surface comprising a flat region having a plurality of three-dimensionally designed surface structures on the flat region;

a nucleation layer composed of oxygen-containing AlN in direct contact with the growth surface at the flat region and the three-dimensionally designed surface structures; and

a nitride-based semiconductor layer sequence on the nucleation layer,

wherein the semiconductor layer sequence overlays the three-dimensionally designed surface structures, and

wherein an oxygen content in the nucleation layer is greater than 10 19 cm −3 .

2. The electronic semiconductor chip according to claim 1 , wherein the nucleation layer is a sputtered layer.

3. The electronic semiconductor chip according to claim 1 , wherein the three-dimensionally designed surface structures are conical or pyramidal elevations on the flat region.

4. The electronic semiconductor chip according to claim 1 , wherein the growth substrate comprises aluminum oxide.

5. The electronic semiconductor chip according to claim 4 , wherein the flat region is a crystallographic c surface.

6. The electronic semiconductor chip according to claim 1 , wherein the growth substrate consists of aluminum oxide.

7. The electronic semiconductor chip according to claim 1 , wherein the semiconductor layer sequence comprises an optoelectronic active layer configured to emit or detect light.

8. The electronic semiconductor chip according to claim 1 , wherein the electronic semiconductor chip is a light-emitting or light-detecting diode.

9. The electronic semiconductor chip according to claim 1 , wherein the nucleation layer is formed by a plurality of posts arranged next to each other which are applied large-scale to the growth surface.

10. The electronic semiconductor chip according to claim 1 , wherein the semiconductor layer sequence is not grown onto the three-dimensionally designed surface structures.

11. A method for producing an electronic semiconductor chip, the method comprising:

providing a growth substrate with a growth surface comprising a flat region having a plurality of three-dimensionally designed surface structures on the flat region;

applying a nucleation layer composed of oxygen-containing AlN directly to the growth surface onto the flat region and the three-dimensionally designed surface structures, wherein an oxygen content in the nucleation layer is greater than 10 19 cm −3 ; and

growing a nitride-based semiconductor layer sequence on the nucleation layer,

wherein the semiconductor layer sequence overlays the three-dimensionally designed surface structures, and

wherein growing the semiconductor layer sequence begins selectively on the flat region.

12. The method according to claim 11 , wherein the nucleation layer is sputtered.

13. The method according to claim 11 , wherein the three-dimensionally designed surface structures comprise conical or pyramidal elevations on the flat region.

14. The method according to claim 11 , wherein the growth substrate comprises aluminum oxide.

15. The method according to claim 14 , wherein the flat region is a crystallographic c surface.

16. The method according to claim 11 , wherein the growth substrate consists of aluminum oxide.

17. The method according to claim 11 , wherein the semiconductor layer sequence comprises an optoelectronic active layer for emitting or detecting light.

18. The method according to claim 11 , wherein the nucleation layer is formed by a plurality of posts arranged next to each other which are applied large-scale to the growth surface.

Assignments (1)
CHANGE OF NAME Recorded Feb 17, 2026
From: OSRAM OPTO SEMICONDUCTORS GMBH
To: AMS-OSRAM INTERNATIONAL GMBH
Reel/Frame 074889/0875 →
Priority Claims (1)
DE 102014101966.0 · Feb 17, 2014 · national
Continuity (4)
Continuation 17206911 · Mar 19, 2021
Continuation 16384550 · Apr 15, 2019
Continuation 15115242
Related Publication 20220344532A1 · Oct 27, 2022