Droop detection
During normal operation of a processor, voltage droop is likely to occur and there is, therefore, a need for techniques for rapidly and accurately detecting this droop so as to reduce the probability of circuit timing failures. The droop detector described herein uses a tap sampled delay line in which a clock signal is split along two separate paths. Each of the taps in the paths are separated by two inverter delays such that the set of samples produced represent sample values of the clock signal that are each separated by a single inverter delay without inversion of the first clock signal between the samples.
1. A method for reactively limiting voltage droop, the method comprising:
providing from a clock generator, a first processor clock signal to a processor for clocking the processor, the first processor clock signal being of a first frequency;
measuring a voltage supplied to the processor to determine an indication of the voltage droop in a voltage supplied to the processor, including measuring a change in a clock edge position of a first clock signal in a tap sampled delay line, wherein the tap sampled delay line is powered by a same power supply that supplies the voltage supplied to the processor;
in response to the indication of the voltage droop, generating a second processor clock signal of a second frequency, wherein the second frequency is lower than the first frequency; and
providing the second processor clock signal to the processor for clocking the processor,
wherein the measuring the change in the clock edge position of the first clock signal in the tap sampled delay line comprises:
producing a set of samples of the first clock signal upon receipt of an edge of a sample clock signal at the tap sampled delay line; and
determining, from the set of samples, the change in the clock edge position of the first clock signal.
2. The method of claim 1 , wherein generating the second processor clock signal comprises:
determining from the indication of the voltage droop that the voltage droop exceeds a threshold; and
in response to the voltage droop exceeding the threshold, removing a proportion of clock pulses from the first processor clock signal.
3. The method of claim 2 , wherein the proportion of clock pulses is dependent upon a magnitude of the voltage droop contained in the indication of the voltage droop.
4. The method of claim 1 , wherein the second frequency (F out ) is related to the first frequency (F in ) by:
F
out
=
N
256
F
i
n
wherein N is an integer.
5. The method of claim 1 , comprising:
propagating the second processor clock signal along copper wires of the processor for clocking a plurality of components of the processor.
6. The method of claim 5 , wherein the copper wires have a thickness of greater than 0.2 micrometres.
7. The method of claim 5 , wherein the plurality of components comprises a plurality of processing units.
8. The method of claim 1 , wherein the first clock signal comprises a delayed version of the sample clock signal.
9. A computer system comprising:
a processor;
a clock generator coupled to the processor and configured to provide a first processor clock signal for clocking the processor, the first processor clock signal having a first frequency; and
clock signal modification circuitry configured to, in response to a voltage droop, generate a second processor clock signal of a second frequency, wherein the second frequency is lower than the first frequency and configured to provide the second processor clock signal to the processor for clocking the processor;
wherein the clock signal modification circuitry comprises means for detecting the voltage droop by measuring a change in a clock edge position of a first clock signal in a tap sampled delay line, including:
means for producing a set of samples of the first clock signal upon receipt of an edge of a sample clock signal at the tap sampled delay line; and
means for determining, from the set of samples, the change in the clock edge position of the first clock signal.
10. The computer system of claim 9 , further comprising:
means for determining that the voltage droop exceeds a threshold;
means for providing an indication that the threshold is exceeded; and
means for removing a proportion of clock pulses in response to the indication that the threshold is exceeded.
11. The computer system of claim 10 , wherein the indication that the threshold is exceeded comprises an indication of the proportion of clock pulses.
12. The computer system of claim 9 , wherein the processor is configured to propagate the second processor clock signal along copper wires of the processor for clocking a plurality of components of the processor.
13. The computer system of claim 12 , wherein the plurality of components comprises a plurality of processing units.
14. The computer system of claim 9 , wherein the clock signal modification circuitry is located at an entry point of the second processor clock signal to the processor.
15. A method comprising:
providing from a clock generator, a first processor clock signal to a processor for clocking the processor, the first processor clock signal being of a first frequency;
detecting a voltage droop in a voltage supplied to the processor, including measuring a change in a clock edge position of a first clock signal in a tap sampled delay line, wherein measuring the change in the clock edge position comprises:
producing a set of samples of the first clock signal upon receipt of an edge of a sample clock signal at the tap sampled delay line, wherein the first clock signal comprises a delayed version of the sample clock signal;
determining, from the set of samples, the change in the clock edge position of the first clock signal;
prior to measuring the change in the clock edge position, receiving the sample clock signal at a further delay line having coarser delay stages than the tap sampled delay line; and
delaying, by the coarser delay stages, the sample clock signal by an amount such that, when a rising edge of the sample clock signal arrives at the tap sampled delay line, a previous rising edge of the sample clock signal is located in the tap sampled delay line;
in response to detecting the voltage droop, generating a second processor clock signal of a second frequency, wherein the second frequency is lower than the first frequency; and
providing the second processor clock signal to the processor for clocking the processor.
16. The method of claim 15 , wherein generating the second processor clock signal comprises:
determining that the voltage droop exceeds a threshold; and
in response to the voltage droop exceeding the threshold, removing a proportion of clock pulses from the first processor clock signal.
17. The method of claim 16 , wherein the proportion of clock pulses is dependent upon a magnitude of the voltage droop.
18. The method of claim 16 , further comprising:
subsequent to removing the proportion of clock pulses, adjusting the second processor clock signal to increase the second frequency, including decreasing the proportion of clock pulses removed from the first processor clock signal.
19. The method of claim 15 , comprising receiving the second processor clock signal at the processor;
propagating the second processor clock signal along wires of the processor for clocking a plurality of components of the processor.
20. The method of claim 19 , wherein the plurality of components of the processor comprises a plurality of processing units.