Isolation structures in multi-gate semiconductor devices and methods of fabricating the same
A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.
1. A semiconductor structure, comprising:
a semiconductor substrate;
an oxide layer disposed over the semiconductor substrate, wherein the oxide layer includes germanium;
a stack of semiconductor layers disposed over the oxide layer; and
an epitaxial source/drain (S/D) feature disposed adjacent to the stack of semiconductor layers and over the oxide layer, wherein a portion of the epitaxial S/D feature is embedded in the oxide layer.
2. The semiconductor structure of claim 1 , wherein the epitaxial S/D feature is a first epitaxial S/D feature, the semiconductor structure further comprising a second epitaxial S/D feature disposed adjacent to the stack of semiconductor layers and over the oxide layer, wherein the oxide layer extends between the first epitaxial S/D feature and the second epitaxial S/D feature.
3. The semiconductor structure of claim 1 , wherein the epitaxial S/D feature is further disposed over a portion of the stack of semiconductor layers.
4. The semiconductor structure of claim 1 , wherein the semiconductor substrate includes elemental silicon.
5. The semiconductor structure of claim 1 , wherein a bottom semiconductor layer of the stack of semiconductor layers and the semiconductor substrate have a same composition.
6. The semiconductor structure of claim 1 , wherein the oxide layer includes silicon oxide, germanium oxide, or a combination thereof.
7. The semiconductor structure of claim 6 , wherein the silicon oxide includes SiOx, where 1≤x≤2.
8. A semiconductor structure, comprising:
a first semiconductor layer, wherein the first semiconductor layer includes elemental Si;
a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer includes silicon oxide, germanium oxide, or a combination thereof;
a third semiconductor layer over the second semiconductor layer, wherein the third semiconductor layer includes elemental Si; and
an epitaxial source/drain (S/D) feature disposed over a portion of the second semiconductor layer and the third semiconductor layer.
9. The semiconductor structure of claim 8 , further comprising a stack of semiconductor layers over the third semiconductor layer.
10. The semiconductor structure of claim 9 , further comprising a gate stack interleaved with the stack of semiconductor layers.
11. The semiconductor structure of claim 8 , wherein the epitaxial S/D feature is in direct contact with the second semiconductor layer.
12. The semiconductor structure of claim 8 , wherein the first semiconductor layer and the third semiconductor layer have a same composition.
13. The semiconductor structure of claim 8 , wherein the epitaxial S/D feature is separated from the first semiconductor layer by the second semiconductor layer.
14. A method, comprising:
forming a germanium-containing layer over a semiconductor layer;
forming a silicon layer over the germanium-containing layer;
performing an implantation process to dope the germanium-containing layer with oxygen;
performing an annealing process to the doped germanium-containing layer to form an oxide layer;
forming channel layers over the oxide layer; and
forming a source/drain (S/D) feature over the oxide layer.
15. The method of claim 14 , further comprising forming a gate stack over the channel layers, wherein the gate stack is disposed between adjacent channel layers and the gate stack is disposed between a bottom one of the channel layers and the silicon layer.
16. The method of claim 14 , wherein the performing the annealing process includes performing a melting laser annealing at or above a melting point of germanium.
17. The method of claim 14 , wherein the forming the S/D feature comprises:
forming an S/D recess that exposes the oxide layer; and
forming the S/D feature in the S/D recess.
18. The method of claim 17 , wherein the forming the S/D recess includes removing a portion of the silicon layer and the oxide layer.
19. The method of claim 14 , further comprising forming a protective layer over the silicon layer before performing the implantation process and removing the protective layer after performing the annealing process.
20. The method of claim 19 , wherein the forming the protective layer includes oxidizing a portion of the silicon layer to form silicon oxide.