Semiconductor device including distributed write driving arrangement
A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells that are connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver and local write drivers included correspondingly in the segments; and the global write driver including a first equalizer circuit, arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line, and the global write driver and the local write drivers each including first inversion couplings (coupled in parallel between the GWB line and the LWB line) and second inversion couplings (coupled in parallel between the GWB_bar line and the LWB_bar line).
1. A semiconductor memory device comprising:
a local write bit (LWB) line;
a local write bit_bar (LWB_bar) line;
a global write bit (GWB) line;
a global write bit_bar (GWB_bar) line;
a column of segments, each segment including bit cells;
each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and
a distributed write driving arrangement including:
a global write driver; and
local write drivers included correspondingly in the segments; and
the global write driver including:
a first equalizer circuit, arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line; and
the global write driver and the local write drivers each including first and second inversion couplings, the first inversion couplings being coupled in parallel between the GWB line and the LWB line, and the second inversion couplings being coupled in parallel between the GWB_bar line and the LWB_bar line.
2. The semiconductor memory device of claim 1 , wherein:
each local write driver is free from having a corresponding equalizer circuit connected between the LWB line and the LWB_bar line.
3. The semiconductor memory device of claim 1 , wherein the first equalizer circuit includes:
a logic-coupling connected between a control input of the switched-coupling and each of the GWB line and the GWB_bar line.
4. The semiconductor memory device of claim 3 , the global write driver further includes:
a transistor connected in series between the LWB line and the LWB_bar line.
5. The semiconductor memory device of claim 4 , wherein:
the logic-coupling is configured to apply a logical OR function to a gate terminal of the transistor.
6. The semiconductor memory device of claim 3 , wherein the first equalizer circuit includes:
a third inversion coupling between the logic-coupling and the switched-coupling.
7. The semiconductor memory device of claim 1 , wherein each of the bit cells includes:
a latch circuit; and
first and second pass gates connecting the corresponding LWB and LWB_bar lines to the latch circuit.
8. The semiconductor memory device of claim 1 , wherein:
each of the bit cells is an eight transistor (8T) type of static random access memory (SRAM) cell.
9. A semiconductor memory device comprising:
a local write bit (LWB) line;
a local write bit_bar (LWB_bar) line;
a global write bit (GWB) line;
a global write bit_bar (GWB_bar) line;
a column of segments, each segment including bit cells;
each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and
a distributed write driving arrangement including:
a global write driver; and
local write drivers included correspondingly in the segments;
the global write driver including:
a first equalizer circuit, arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line; and
the global write driver and the local write drivers each including first and second inversion couplings, the first inversion couplings being coupled in parallel between the GWB line and the LWB line, and the second inversion couplings being coupled in parallel between the GWB_bar line and the LWB_bar line; and
each local write driver is free from having a corresponding equalizer circuit connected between the LWB line and the LWB_bar line.
10. The semiconductor memory device of claim 9 , wherein the first equalizer circuit includes:
a logic-coupling connected between a control input of the switched-coupling and each of the GWB line and the GWB_bar line.
11. The semiconductor memory device of claim 10 , the global write driver further includes:
a transistor connected in series between the LWB line and the LWB_bar line.
12. The semiconductor memory device of claim 11 , wherein:
the logic-coupling is configured to apply a logical OR function to a gate terminal of the transistor.
13. The semiconductor memory device of claim 10 , wherein the first equalizer circuit includes:
a third inversion coupling between the logic-coupling and the switched-coupling.
14. The semiconductor memory device of claim 9 , wherein each of the bit cells includes:
a latch circuit; and
first and second pass gates connecting the corresponding LWB and LWB_bar lines to the latch circuit.
15. The semiconductor memory device of claim 9 , wherein:
each of the bit cells is an eight transistor (8T) type of static random access memory (SRAM) cell.
16. A semiconductor memory device comprising:
a local write bit (LWB) line;
a local write bit_bar (LWB_bar) line;
a global write bit (GWB) line;
a global write bit_bar (GWB_bar) line;
a column of segments, each segment including bit cells, each of the bit cells being an eight transistor (8T) type of static random access memory (SRAM) cell;
each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and
a distributed write driving arrangement including:
a global write driver; and
local write drivers included correspondingly in the segments;
the global write driver including:
a first equalizer circuit, arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line; and
the global write driver and the local write drivers each including first and second inversion couplings, the first inversion couplings being coupled in parallel between the GWB line and the LWB line, and the second inversion couplings being coupled in parallel between the GWB_bar line and the LWB_bar line.
17. The semiconductor memory device of claim 16 , wherein:
each local write driver is free from having a corresponding equalizer circuit connected between the LWB line and the LWB_bar line.
18. The semiconductor memory device of claim 16 , wherein the first equalizer circuit includes:
a logic-coupling connected between a control input of the switched-coupling and each of the GWB line and the GWB_bar line.
19. The semiconductor memory device of claim 18 , the global write driver further includes:
a transistor connected in series between the LWB line and the LWB_bar line.
20. The semiconductor memory device of claim 16 , wherein each of the bit cells includes:
a latch circuit; and
first and second pass gates connecting the corresponding LWB and LWB_bar lines to the latch circuit.