Manufacturing method of semiconductor structure and semiconductor structure
View Patent ↗The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars arranged in an array on the substrate; pre-processing the silicon pillar, to form an active pillar, where along a first direction, the active pillar includes a first segment, a second segment, and a third segment that are connected sequentially; forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and forming a gate dielectric layer on the gate oxide layer, where along the first direction, the gate dielectric layer is shorter than the gate oxide layer, and a top surface of the gate dielectric layer is flush with that of the third segment.
1. A manufacturing method of a semiconductor structure, comprising:
providing a substrate;
forming a plurality of silicon pillars on the substrate, wherein the plurality of silicon pillars are arranged as an array;
pre-processing the silicon pillar to form an active pillar, wherein along a first direction, the active pillar comprises a first segment, a second segment, and a third segment that are connected sequentially;
forming a gate oxide layer on sidewalls of each of the second segment and the third segment; and
forming a gate dielectric layer on the gate oxide layer, wherein along the first direction, the gate dielectric layer is shorter than the gate oxide layer, and a top surface of the gate dielectric layer is flush with that of the third segment;
wherein the forming a plurality of silicon pillars on the substrate comprises:
forming a plurality of bit line isolation trenches in the substrate, wherein the plurality of bit line isolation trenches are arranged at intervals along a second direction, and the substrate between adjacent two of the bit line isolation trenches forms a strip body; and
forming a plurality of word line isolation trenches in the substrate, wherein the plurality of word line isolation trenches are arranged at intervals along a third direction to divide the strip body into the plurality of silicon pillars, and along the first direction, the word line isolation trench is shallower than the bit line isolation trench.
2. The manufacturing method of a semiconductor structure according to claim 1 , wherein the pre-processing the silicon pillar to form an active pillar comprises:
oxidizing the silicon pillar, wherein a plane perpendicular to the first direction is used as a cross section, and a cross-sectional shape of the active pillar comprises a circle.
3. The manufacturing method of a semiconductor structure according to claim 1 , the manufacturing method further comprises:
forming a first isolation layer in the bit line isolation trench, wherein a top surface of the first isolation layer is flush with a bottom surface of the word line isolation trench; and
implanting ions into the word line isolation trenches, to form a plurality of bit lines at bottom surfaces of the first segments, wherein the plurality of bit lines are arranged at intervals along the second direction.
4. The manufacturing method of a semiconductor structure according to claim 3 , the manufacturing method further comprises:
forming a plurality of bit line isolation structures in the substrate, wherein the plurality of bit line isolation structures are arranged at intervals along the second direction.
5. The manufacturing method of a semiconductor structure according to claim 4 , wherein the forming a plurality of bit line isolation structures in the substrate comprises:
forming a second initial isolation layer on the top surface of the first isolation layer and in the word line isolation trench; and
partially removing the second initial isolation layer along the first direction, wherein the retained second initial isolation layer forms a second isolation layer; and
along the first direction, the first isolation layer and the second isolation layer in the bit line isolation trench form the bit line isolation structure, and a top surface of the second isolation layer is flush with a junction between the first segment and the second segment.
6. The manufacturing method of a semiconductor structure according to claim 5 , wherein the forming a gate oxide layer on sidewalls of each of the second segment and the third segment comprises:
forming an initial gate oxide layer on the active pillar by an atomic layer deposition process, wherein the initial gate oxide layer covers the sidewall of the second segment, and the sidewall and the top surface of the third segment; and
partially removing the initial gate oxide layer, to expose the top surface of the second isolation layer, wherein the retained initial gate oxide layer forms the gate oxide layer.
7. The manufacturing method of a semiconductor structure according to claim 6 , wherein a filling region is formed between the top surface of the second isolation layer and a sidewall of the gate oxide layer; and
the forming a gate dielectric layer on the gate oxide layer comprises:
forming a first initial word line in the filling region;
partially removing the first initial word line, wherein the retained first initial word line forms a first word line, a top surface of the first word line is flush with a preset position of the second segment, and a first trench is formed between the first word line and the gate oxide layer adjacent thereto;
removing the gate oxide layer on the top surface of the third segment; and
forming the gate dielectric layer on a sidewall of the first trench.
8. The manufacturing method of a semiconductor structure according to claim 7 , wherein a second trench is formed between the top surface of the first word line and a sidewall of the gate dielectric layer; and
the manufacturing method of a semiconductor structure further comprises:
forming a second initial word line in the second trench; and
partially removing the second initial word line, wherein the retained second initial word line forms a second word line, a top surface of the second word line is flush with a junction between the second segment and the third segment, and the first word line and the second word line form an initial word line structure.
9. The manufacturing method of a semiconductor structure according to claim 8 , the manufacturing method further comprises:
forming a third initial isolation layer on the initial word line structure;
partially removing the third initial isolation layers and the initial word line structures, to form a plurality of third trenches arranged at intervals along the third direction on the substrate, wherein a bottom of the third trench exposes the second isolation layer, and the plurality of third trenches correspond to the plurality of initial word line structures one by one; and
forming a fourth isolation layer in the third trench, wherein
the retained initial word line structure forms two word lines, the retained third initial isolation layer forms a third isolation layer, and the third isolation layer and the fourth isolation layer form a word line isolation structure.
10. The manufacturing method of a semiconductor structure according to claim 6 , wherein a filling region is formed between the top surface of the second isolation layer and a sidewall of the gate oxide layer; and
the forming a gate dielectric layer on the gate oxide layer comprises:
forming a sacrificial layer in the filling region, wherein a top surface of the sacrificial layer is flush with a preset position of the second segment;
partially removing the gate oxide layer, to expose a top surface of the active pillar;
forming the gate dielectric layer, wherein a bottom surface of the gate dielectric layer is connected to the top surface of the sacrificial layer, and the gate dielectric layer is located outside the gate oxide layer partially covering the sidewalls of each of the second segment and the third segment; and
removing the sacrificial layer, wherein a sidewall of the gate dielectric layer and the sidewall of the gate oxide layer originally covered by the sacrificial layer form a fourth trench.
11. The manufacturing method of a semiconductor structure according to claim 10 , the manufacturing method further comprises:
forming a plurality of word line isolation structures in the fourth trenches, wherein the plurality of word line isolation structures are arranged at intervals along the third direction.
12. The manufacturing method of a semiconductor structure according to claim 11 , wherein the forming a plurality of word line isolation structures in the fourth trenches comprises:
forming a plurality of initial word lines in the fourth trenches, wherein the plurality of initial word lines are arranged at intervals along the third direction;
partially removing the initial word line along the first direction, wherein the retained initial word line forms an intermediate word line, and a fifth trench is formed between the intermediate word line and the sidewall of the gate dielectric layer;
forming a fifth initial isolation layer in the fifth trench;
partially removing the fifth initial isolation layers and the intermediate word lines along the first direction, to form a plurality of sixth trenches arranged at intervals along the third direction, wherein a bottom of the sixth trench exposes the top surface of the second isolation layer, the retained fifth initial isolation layer forms a fifth isolation layer, and the retained intermediate word line forms two word lines; and
forming a sixth isolation layer in the sixth trench, wherein the sixth isolation layer and the fifth isolation layer form the word line isolation structure.