High density access transistor having increased channel width and methods of fabricating such devices
A memory device having decreased cell size and having transistors with increased channel widths. More specifically, pillars are formed in a substrate such that sidewalls are exposed. The sidewalls of the pillars and the top surface of the pillars are covered with a gate oxide and a polysilicon layer to form a channel through the pillars. The current path through the channel is approximately equal to twice the height of the pillar plus the width of the pillar. The pillars are patterned to form non-linear active area lines having angled segments. The polysilicon layer is patterned to from word lines that intersect the active area lines at the angled segments.
1. A method of fabricating a memory device comprising:
etching deep trenches in a silicon substrate to form continuous silicon pillars that weave in a direction parallel to the surface of the substrate;
depositing an isolation material into the deep trenches to completely fill the deep trenches;
etching shallow trenches in the isolation material such that a portion of the silicon pillars extend from the planar surface of the isolation material;
forming a gate oxide on a top surface of the silicon pillars and along sidewalls of the silicon pillars; and
depositing a conductive layer, such that the conductive layer fills the shallow trenches and completely covers the gate oxide.
2. The method, as set forth in claim 1 , wherein etching deep trenches comprises etching trenches having a depth in the range of approximately 3,000-12,000 angstroms.
3. The method, as set forth in claim 1 , wherein etching shallow trenches comprises etching trenches having a depth in the range of approximately 400-10,000 angstroms.
4. The method, as set forth in claim 1 , wherein etching shallow trenches to form continuous silicon pillars comprises etching trenches comprising first segments formed at an angle with respect to second segments of the trenches.
5. The method, as set forth in claim 1 , wherein etching shallow trenches to form continuous silicon pillars comprises etching trenches comprising first segments formed at an angle with respect to second segments of the trenches, wherein the angle is greater than 0° and less than or equal to approximately 45°.
6. The method, as set forth in claim 1 , wherein forming a gate oxide comprises growing the gate oxide.
7. The method, as set forth in claim 1 , wherein depositing the isolation material comprises depositing an oxide into the deep trenches.
8. The method, as set forth in claim 1 , wherein depositing the isolation material comprises depositing a spin-on dielectric into the deep trenches.
9. A method of fabricating a memory device comprising:
etching trenches in a top silicon layer of a silicon on insulator substrate to form continuous silicon pillars that weave in a direction parallel to the surface of the substrate;
forming a gate oxide on a top surface of the silicon pillars and along sidewalls of the silicon pillars;
depositing a high-k dielectric material on the gate oxide; and
depositing a conductive layer, such that the conductive layer fills the shallow trenches and completely covers the gate oxide.
10. The method, as set forth in claim 9 , wherein etching trenches comprises etching trenches having a depth in the range of approximately 200-3,000 angstroms.
11. The method, as set forth in claim 9 , wherein etching shallow trenches to form continuous silicon pillars comprises etching trenches comprising first segments formed at an angle with respect to second segments of the trenches.
12. The method, as set forth in claim 9 , wherein etching shallow trenches to form continuous silicon pillars comprises etching trenches comprising first segments formed at an angle with respect to second segments of the trenches, wherein the angle is greater than 0° and less than or equal to approximately 45°.
13. The method, as set forth in claim 9 , wherein forming a gate oxide comprises growing the gate oxide.
14. The method, as set forth in claim 9 , wherein depositing the conductive layer comprises depositing a polysilicon layer.
15. The method, as set forth in claim 9 , wherein depositing the conductive layer comprises depositing a metal layer.
16. The method, as set forth in claim 9 , wherein depositing the conductive layer comprises depositing a silicon germanium (SiGe) layer.
17. A method of fabricating an integrated circuit comprising the acts of:
forming a plurality of continuous pillars in a substrate material, the pillars extending from the surface of the substrate and forming an array of non-linear rows, wherein each of the non-linear rows are parallel to the surface of the substrate and have a plurality of a plurality of first segments extending in a first direction, a plurality of second segments extending in a second direction and a plurality of third segments extending in a third direction, wherein the first direction and the third direction are complimentary directions and where in the first and third directions are different from that second direction;
forming a gate oxide along a top surface and sidewalls of the plurality of pillars; and
disposing a conductive layer to completely cover the gate oxide.
18. The method, as set forth in claim 17 , wherein forming the plurality of pillars comprises forming a plurality of channels of a transistor.
19. The method, as set forth in claim 18 , wherein forming the plurality of channels comprises forming the plurality of channels having a current path equal to approximately two times a height of the pillars plus the width of the pillars.
20. The method, as set forth in claim 17 , wherein forming the plurality of pillars in a substrate material comprises forming a plurality of pillars in a bulk silicon substrate.
21. The method, as set forth in claim 17 , wherein forming the plurality of pillars in a substrate material comprises forming a plurality of pillars in a silicon on insulator (SOI) substrate.
22. The method, as set forth in claim 17 , wherein forming the plurality of pillars in a substrate material comprises forming a plurality of pillars in a silicon germanium (SiGe) substrate.
23. The method, as set forth in claim 17 , wherein disposing a polysilicon layer comprises forming a word line in a memory array.
24. The method, as set forth in claim 23 , wherein forming a word line comprises forming a word line which intersects the plurality of continuous pillars non-orthogonally.