Asymmetric memory cell design
Methods, systems, and devices for asymmetric memory cell design are described. A memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget. For example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.
1. An apparatus, comprising:
a memory cell comprising a storage material between and in contact with a first surface of a first dielectric layer and a second surface of a second dielectric layer;
a first access line decoder coupled with the memory cell via a first electrode, the first electrode coupled with the storage material via a first contact area extending between the first surface of the first dielectric layer and the second surface of the second dielectric layer; and
a second access line decoder coupled with the memory cell via a second electrode, the second electrode extending into a recess of the storage material between the first surface of the first dielectric layer and the second surface of the second dielectric layer, and the second electrode in contact with a third surface of the first dielectric layer and a fourth surface of the second dielectric layer.
2. The apparatus of claim 1 , wherein the second electrode is coupled with the storage material via a second contact area, and a first dimension of the first contact area is greater than the first dimension of the second contact area.
3. The apparatus of claim 1 , wherein:
the first electrode comprises carbon, tungsten, titanium nitride, a transition metal, or any combination thereof, and
the second electrode comprises carbon, tungsten, titanium nitride, a transition metal, or any combination thereof.
4. The apparatus of claim 1 , wherein the storage material comprises a chalcogenide material.
5. The apparatus of claim 1 , wherein the second electrode is coupled with the storage material via a second contact area at an end of the recess of the storage material that is smaller than the first contact area.
6. The apparatus of claim 1 , wherein the second access line decoder is coupled with the memory cell via a third electrode coupled with the second electrode.
7. An apparatus, comprising:
a set of memory cells, each memory cell comprising a respective portion of a storage material between and in contact with a respective first surface of a first dielectric layer and a respective second surface of a second dielectric layer;
a set of first access lines, each first access line coupled with a respective memory cell of the set of memory cells via a first electrode of a plurality of first electrodes, a respective first electrode coupled with the respective portion of the storage material of the respective memory cell via a first contact area extending between the respective first surface of the first dielectric layer and the respective second surface of the second dielectric layer; and
a second access line coupled with each memory cell of the set of memory cells via a second electrode of a plurality of second electrodes, a respective second electrode extending into a respective recess of the storage material between the respective first surface of the first dielectric layer and the respective second surface of the second dielectric layer, and the respective second electrode in contact with a respective third surface of the first dielectric layer and a fourth surface of the second dielectric layer.
8. The apparatus of claim 7 , wherein the respective second electrode is coupled with the respective portion of the storage material via a second contact area, and a first dimension of the first contact area is greater than the first dimension of the second contact area.
9. The apparatus of claim 7 , further comprising:
a dielectric material between a first memory cell of the set of memory cells and a second memory cell of the set of memory cells.
10. The apparatus of claim 7 , wherein:
the set of first access lines are coupled with a word line decoder; and
the second access line is coupled with a bit line decoder.
11. The apparatus of claim 7 , wherein:
each first electrode comprises carbon, tungsten, titanium nitride, a transition metal, or any combination thereof, and
each second electrode comprises carbon, tungsten, titanium nitride, a transition metal, or any combination thereof.
12. The apparatus of claim 7 , wherein the storage material comprises a chalcogenide material.
13. The apparatus of claim 7 , wherein the respective second electrode is coupled with the respective portion of the storage material via a second contact area at an end of the respective recess of the storage material that is smaller than the first contact area.
14. The apparatus of claim 7 , wherein the second access line is coupled with each memory cell of the set of memory cells via a third electrode of a plurality of third electrodes, a respective third electrode coupled with the respective second electrode.