Half-bridge circuit using separately packaged GaN power devices
GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.
1. A circuit, comprising:
a low-side circuit disposed on a first semiconductor die, the first semiconductor die formed from at least one layer of gallium-nitride disposed on a layer of silicon, wherein the low-side circuit comprises:
a low-side switch comprising a low-side switch control gate, a low-side source, and a low-side drain;
a low-side driver circuit coupled to the low-side switch control gate and arranged to control a conductivity state of the low-side switch in response to receiving a first input signal;
wherein the first semiconductor die is disposed within a first electronic package that includes a first die-attach pad attached to the first semiconductor die and a plurality of first external terminals electrically connected to the first semiconductor die via one or more first wirebonds and wherein the first die-attach pad and the plurality of first external terminals are positioned on a first common plane; and
a high-side circuit disposed on a second semiconductor die, the second semiconductor die formed from at least one layer of gallium-nitride disposed on a layer of silicon, wherein the high-side circuit comprises:
a high-side switch comprising a high-side switch control gate, a high-side source, and a high-side drain;
a high-side driver circuit coupled to the high-side switch control gate and arranged to control a conductivity state of the high-side switch in response to receiving a second input signal;
wherein the second semiconductor die is disposed within a second electronic package that includes a second die-attach pad attached to the second semiconductor die and a plurality of second external terminals electrically connected to the second semiconductor die via one or more second wirebonds and wherein the second die-attach pad and the plurality of second external terminals are positioned on a second common plane;
wherein the low-side drain is electrically connected to the high-side source forming a half-bridge circuit.
2. The circuit of claim 1 wherein the first and second electronic packages are quad-flat no-lead electronic packages.
3. The circuit of claim 1 further comprising a first mold compound at least partially encapsulating the first semiconductor die and a second mold compound at least partially encapsulating the second semiconductor die.
4. The circuit of claim 1 wherein the at least one layer of gallium-nitride comprises a composite stack of III-nitride layers.
5. The circuit of claim 1 wherein the at least one layer of gallium-nitride comprises a layer of aluminum gallium nitride.
6. The circuit of claim 1 wherein the low-side switch and the high-side switch are each enhancement-mode transistors.
7. The circuit of claim 1 further comprising a level-shift circuit electrically coupled to the high-side driver circuit.
8. The circuit of claim 1 wherein the low-side drain and the high-side source are electrically connected through the plurality first external terminals and the plurality of second external terminals.
9. A half-bridge circuit, comprising:
a low-side circuit disposed on one or more gallium-nitride layers of a first semiconductor device, wherein the low-side circuit comprises:
a low-side transistor comprising a low-side transistor control gate, a low-side source, and a low-side drain wherein the low-side transistor is controlled by a low-side transistor driver circuit arranged to change a conductivity state of the low-side transistor in response to receiving a first input signal;
wherein the first semiconductor device is disposed within a first electronic package that includes a first die-attach pad attached to the first semiconductor device and a plurality of first external terminals electrically connected to the first semiconductor device via one or more first wirebonds and wherein the first die-attach pad and the plurality of first external terminals are positioned on a first common plane; and
a high-side circuit disposed on one or more gallium-nitride layers of a second semiconductor device, wherein the high-side circuit comprises:
a high-side transistor comprising a high-side transistor control gate, a high-side source, and a high-side drain wherein the high-side transistor is controlled by a high-side transistor driver circuit arranged to change a conductivity state of the high-side transistor in response to receiving a second input signal;
wherein the second semiconductor device is disposed within a second electronic package that includes a second die-attach pad attached to the second semiconductor device and a plurality of second external terminals electrically connected to the second semiconductor device via one or more second wirebonds and wherein the second die-attach pad and the plurality of second external terminals are positioned on a second common plane;
wherein the low-side drain is electrically connected to the high-side source forming a switch node of the half-bridge circuit.
10. The half-bridge circuit of claim 9 wherein the first and second electronic packages are quad-flat no-lead electronic packages.
11. The half-bridge circuit of claim 9 wherein the one or more gallium-nitride layers comprises a composite stack of III-nitride layers.
12. The half-bridge circuit of claim 9 wherein the low-side transistor and the high-side transistor are each enhancement-mode transistors.
13. The half-bridge circuit of claim 9 further comprising a level-shift circuit electrically coupled to the high-side transistor driver circuit.
14. The half-bridge circuit of claim 9 wherein the low-side drain and the high-side source are electrically connected through the plurality first external terminals and through the plurality of second external terminals.
15. The half-bridge circuit of claim 9 wherein the low-side transistor driver circuit is disposed on the first semiconductor device.
16. The half-bridge circuit of claim 9 wherein the low-side transistor driver circuit is disposed on a third semiconductor device.
17. The half-bridge circuit of claim 9 wherein the high-side transistor driver circuit is disposed on the second semiconductor device.
18. A half-bridge power converter, comprising:
a low-side circuit disposed on a first semiconductor device, the first semiconductor device formed from a first semiconductor substrate comprising gallium-nitride, wherein the low-side circuit comprises:
a low-side transistor comprising a low-side switch control gate, a low-side source, and a low-side drain wherein the low-side transistor is controlled by a low-side transistor driver circuit arranged to control a conductivity state of the low-side transistor in response to receiving a first input signal;
wherein the first semiconductor device is attached to a first die-attach pad and is electrically coupled to a plurality of first terminals via one or more first wirebonds, the plurality of first terminals formed within a first common plane;
a high-side circuit disposed on a second semiconductor device, the second semiconductor device formed from a second semiconductor substrate comprising gallium-nitride, wherein the high-side circuit comprises:
a high-side transistor comprising a high-side switch control gate, a high-side source, and a high-side drain wherein the high-side transistor is controlled by a high-side transistor driver circuit arranged to control a conductivity state of the high-side transistor in response to receiving a second input signal;
wherein the second semiconductor device is attached to a second die-attach pad and is electrically coupled to a plurality of second terminals via one or more second wirebonds, the plurality of second terminals formed within a second common plane;
wherein the low-side drain is electrically connected to the high-side source forming a switch-node of the half-bridge power converter.
19. The half-bridge power converter of claim 18 wherein the low-side drain and the high-side source are electrically connected via the plurality first terminals and the plurality of second terminals.
20. The half-bridge power converter of claim 18 wherein the low-side transistor driver circuit is disposed on a third semiconductor device.