Half-bridge circuit using GaN power devices
GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.
1. A half bridge circuit, comprising:
a low side circuit disposed in gallium-nitride and comprising:
a low side switch comprising a low side switch control gate, a first source, and a first drain;
a low side switch driver that controls a conductivity state of the low side switch according to a first input signal; and
a level shift circuit;
a high side circuit disposed in gallium-nitride and comprising:
a high side switch comprising a high side switch control gate, a second source, and a second drain, wherein the second source is connected to the first drain, and
a high side switch driver referenced to a voltage at the second source, wherein the high side switch driver controls a conductivity state of the high side switch according to a second input signal and wherein the high side switch driver is configured to prevent a change of conductivity state of the high side switch in response to voltage transients of the voltage at the second source;
wherein the level shift circuit generates a level shift signal to control an output state of the high side switch driver in response to receiving the second input signal.
2. The half bridge circuit of claim 1 , wherein the high side circuit further comprises a receiver circuit configured to receive the level shift signal and to generate a receiver output signal that controls the output state of the high side switch driver.
3. The half bridge circuit of claim 1 , wherein the low side circuit is formed on a first semiconductor die and wherein the high side circuit is formed on a second semiconductor die.
4. The half bridge circuit of claim 3 , wherein the first semiconductor die and the second semiconductor die are flip-chips.
5. The half bridge circuit of claim 3 , wherein the first semiconductor die is disposed within a first electronic package and wherein the second semiconductor die is disposed within a second electronic package.
6. The half bridge circuit of claim 1 , wherein the low side circuit and the high side circuit are formed on a single monolithic semiconductor die.
7. The half bridge circuit of claim 6 , wherein the single monolithic semiconductor die is a flip-chip.
8. The half bridge circuit of claim 1 , wherein the gallium-nitride comprises one or more layers of gallium-nitride disposed on a layer of silicon.
9. A half bridge circuit, comprising:
a low side circuit formed from gallium-nitride and comprising:
a low side switch comprising a low side switch control gate, a first source, and a first drain; and
a low side switch driver, configured to control a conductivity state of the low side switch according to a first input signal;
a high side circuit formed from gallium-nitride and comprising:
a high side switch comprising a high side switch control gate, a second source, and a second drain, wherein the second source is connected to the first drain; and
a high side switch driver referenced to a voltage at the second source, wherein the high side switch driver controls a conductivity state of the high side switch according to a plurality of pulses, and wherein durations of on and off times of the high side switch are based on durations of the plurality of pulses;
wherein the low side circuit further comprises a level shift circuit configured to generate the plurality of pulses in response to a second input signal.
10. The half bridge circuit of claim 9 , wherein the low side circuit is formed on a first semiconductor die and wherein the high side circuit is formed on a second semiconductor die.
11. The half bridge circuit of claim 10 , wherein the first semiconductor die and the second semiconductor die are flip-chips.
12. The half bridge circuit of claim 10 , wherein the first semiconductor die is disposed within a first electronic package and wherein the second semiconductor die is disposed within a second electronic package.
13. The half bridge circuit of claim 9 , wherein the low side circuit and the high side circuit are formed on a single monolithic semiconductor die.
14. The half bridge circuit of claim 13 , wherein the single monolithic semiconductor die is a flip-chip.
15. The half bridge circuit of claim 9 , wherein the gallium-nitride comprises one or more layers of gallium-nitride disposed on a layer of silicon.
16. A circuit, comprising:
a low side GaN-based circuit comprising:
a low side switch comprising a low side switch control gate, a first source, and a first drain;
a low side switch driver, configured to control a conductivity state of the low side switch according to a first input signal; and
a level shift circuit;
a high side GaN-based circuit comprising:
a high side switch comprising a high side switch control gate, a second source, and a second drain, wherein the second source is connected to the first drain; and
a high side switch driver referenced to a voltage at the second source, wherein the high side switch driver controls a conductivity state of the high side switch according to a second input signal; and
wherein in response to receiving the second input signal, the level shift circuit generates a level shift signal that controls an output state of the high side switch driver.
17. The circuit of claim 16 , wherein the low side GaN-based circuit is formed on a first semiconductor die and wherein the high side GaN-based circuit is formed on a second semiconductor die.
18. The circuit of claim 17 , wherein the first semiconductor die and the second semiconductor die are flip-chips.
19. The circuit of claim 17 , wherein the first semiconductor die is disposed within a first electronic package and wherein the second semiconductor die is disposed within a second electronic package.
20. The circuit of claim 16 , wherein the low side circuit and the high side circuit are formed on a single monolithic semiconductor die.