IP Library Patent Application 17822403
Patent Application
App. No. 17/822,403

IMAGE SENSOR BALL GRID ARRAY PACKAGE

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Quick Facts
Patent No.
US None
App. No.
17/822,403
Abstract

A package includes an interposer substrate having at least one through-substrate via (TSV) electrically connecting a top surface of the interposer substrate to a bottom surface of the interposer substrate. The package further includes at least one semiconductor die having a top side, a bottom side, and a sidewall. The at least one semiconductor die is disposed on the interposer substrate with the bottom side electrically coupled to the top surface of the interposer substrate. A molding material is disposed on at least on a portion of the at least one semiconductor die, and an array of conductive material is disposed on the bottom surface of the interposer substrate. The array of conductive material forms the external contacts of the package.

Claims (50)

1 . A package comprising:

an interposer substrate including at least one through-substrate via (TSV) electrically connecting a top surface of the interposer substrate to a bottom surface of the interposer substrate;

at least one semiconductor die having a top side, a bottom side, and a sidewall, the at least one semiconductor die being disposed on the interposer substrate with the bottom side electrically coupled to the top surface of the interposer substrate;

a molding material disposed on at least on a portion of the at least one semiconductor die; and

an array of conductive material disposed on the bottom surface of the interposer substrate, the array of conductive material forming external contacts of the package.

2 . The package of claim 1 , wherein at least one semiconductor die has a width, and the interposer substrate has a width that is greater than the width of the at least one semiconductor die.

3 . The package of claim 1 , wherein at least one semiconductor die is an optical sensor die, and the package further includes a glass cover disposed above the top side of the optical sensor die.

4 . The package of claim 3 further comprising:

a non-transparent black coating disposed on an edge portion of the glass cover disposed above the top side of the optical sensor die.

5 . The package of claim 1 , wherein the array of conductive material disposed on the bottom surface of the interposer substrate is a ball grid array of solder.

6 . The package of claim 1 , wherein the at least one semiconductor die is a stack of an optical sensor die disposed above an application-specific integrated circuit (ASIC) die, the ASIC die including at least one backside through-semiconductor via (BTSV) for electrical connections to the optical sensor die.

7 . A package comprising:

an interposer substrate including at least one through-substrate via electrically connecting a top surface of the interposer substrate to a bottom surface of the interposer substrate;

at least one semiconductor die disposed on the interposer substrate with a bottom side of the at least one semiconductor die being electrically coupled to the top surface of the interposer substrate;

a layer of molding material disposed on the bottom surface of the interposer substrate, the layer of molding material including at least one through-mold via for electrical connection to the interposer substrate;

an image signal processing (ISP) die embedded in the layer of molding material; and

an array of conductive material disposed on a bottom surface of the layer of molding material, the array of conductive material forming external contacts of the package.

8 . The package of claim 7 , wherein the image signal processing (ISP) die embedded in the layer of molding material is flip chip mounted on the bottom surface of the interposer substrate.

9 . The package of claim 7 , wherein the at least one semiconductor die has a width, and the interposer substrate has a width that is greater than the width of the at least one semiconductor die.

10 . The package of claim 7 , wherein at least one semiconductor die is an optical sensor die, and the package further includes a glass cover disposed above a top side of the optical sensor die.

11 . The package of claim 10 further comprising:

a non-transparent black coating disposed on an edge portion of the glass cover disposed above the top side of the optical sensor die.

12 . The package of claim 7 , wherein the array of conductive material disposed on the bottom surface of the interposer substrate is a ball grid array of solder.

13 . The package of claim 7 , wherein the at least one semiconductor die is a stack of an optical sensor die disposed above an application-specific integrated circuit (ASIC) die, the ASIC die including at least one backside through-semiconductor via (BTSV) for electrical connections to the optical sensor die.

14 . A method, comprising:

disposing a stack of semiconductor die on a top surface of an interposer substrate, the top surface of the interposer substrate including contact pads;

disposing contact pads on a bottom surface of the interposer substrate;

electrically connecting the contact pads on the top surface of interposer substrate and the contact pads on the bottom surface of the interposer substrate; and

disposing an array of conductive material on the contact pads on the bottom surface of the interposer substrate, the array of conductive material forming external contacts of the stack of the semiconductor die.

15 . The method of claim 14 further comprising:

disposing molding material on at least four sides of the stack of the semiconductor die to encapsulate the stack of the semiconductor die disposed on the top surface of the interposer substrate.

16 . The method of claim 15 further comprising:

singulating the interposer substrate with the stack of the semiconductor die disposed encapsulated thereon to isolate an individual optical sensor package including the stack of the semiconductor die encapsulated by the molding material.

17 . The method of claim 16 , singulating the interposer substrate with the encapsulated stack of the semiconductor die encapsulated thereon includes singulating through pre-identified saw street areas on the interposer substrate.

18 . The method of claim 14 , wherein disposing the stack of the semiconductor die on the top surface of an interposer substrate includes bonding the stack of the semiconductor die to the contact pads on the top surface of interposer substrate using the array of conductive material disposed on the bottom surface of the stack of the semiconductor die.

19 . The method of claim 14 , wherein electrically connecting the contact pads on the top surface of interposer substrate and the contact pads on the bottom surface of the interposer substrate includes utilizing at least one through-substrate via for electrically connecting the top surface of interposer substrate and the bottom surface of the interposer substrate.

20 . The method of claim 14 , wherein the stack of the semiconductor die includes a glass cover placed above an optical sensor die and the method further includes disposing a non-transparent black coating on an edge portion of at least one of a top surface or a bottom surface of the glass cover.

21 . A method comprising:

disposing a stack of semiconductor die on a top surface of an interposer substrate, the stack of the semiconductor die including an optical sensor die and an application-specific integrated circuit (ASIC) die;

disposing a molding material to encapsulate the stack of the semiconductor die including the optical sensor die and the ASIC die on the top surface of the interposer substrate, the molding material being disposed on four sides of the stack of the semiconductor die above the top surface of interposer substrate and filling in saw street areas of the interposer substrate that have been etched to a depth below the top surface of the interposer substrate;

thinning the interposer substrate from a backside to expose the molding material filling the saw street areas on a back surface of the interposer substrate;

disposing contact pads on the back surface of the interposer substrate;

attaching an image signal processor (ISP) die to the back surface of the interposer substrate;

disposing an array of conductive material on contact pads not used by the ISP die on a bottom surface of the interposer substrate;

disposing a layer of molding material on the bottom surface of the interposer substrate such that the ISP die, and the array of conductive material disposed the backside of the interposer substrate are embedded in the layer of molding material;

thinning the layer of molding material disposed on the bottom surface of the interposer substrate from the backside to expose elements of the embedded array of conductive material on a bottom surface of the layer of molding material;

augmenting the elements of the embedded array of conductive material exposed on the bottom surface of the layer of molding with additional conductive material, the embedded array of conductive material forming external input/output contacts of the stack of the semiconductor die; and

singulating the interposer substrate (with the encapsulated stack of the optical sensor die and the ASIC die, and the ISP die disposed thereon) to isolate an individual optical sensor package including the optical sensor die, the ASIC die, and the ISP die encapsulated by the molding material.

22 . The method of claim 21 , wherein singulating the interposer substrate with encapsulated stack of the optical sensor die and the ASIC die, and the ISP die disposed thereon includes singulating through pre-identified saw street areas on the interposer substrate that are filled with the molding material.

23 . The method of claim 21 , wherein thinning the interposer substrate from the backside to expose the molding material filling the saw street areas on the back surface of the interposer substrate includes exposing at least one through-substrate via present in the interposer substrate on the back surface of the interposer substrate.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 061879, FRAME 0655 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: FAIRCHILD SEMICONDUCTOR CORPORATION; SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 064123/0001 →
SECURITY INTEREST Recorded Nov 3, 2022
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 061879/0655 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2022
From: LIN, YUSHENG; BORTHAKUR, SWARNAL; KINSMAN, LARRY DUANE
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 061388/0354 →