IP Library › Granted Patent US 12,342,583
Granted Patent B2
US 12,342,583 · App. 17/822,949 · Granted Jun 24, 2025

Semiconductor device, inverter circuit, drive device, vehicle, and elevator

Inventors: Teruyuki Ohashi (Kawasaki, JP); Hiroshi Kono (Himeji, JP); Shunsuke Asaba (Himeji, JP); Takahiro Ogata (Kobe, JP)
Assignee: KABUSHIKI KAISHA TOSHIBA
H10D62/106H02P27/06H10D62/157H10D62/8325
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Quick Facts
Patent No.
US 12,342,583
App. No.
17/822,949
Granted
Jun 24, 2025
Kind
B2
Abstract

A semiconductor device of an embodiment includes a transistor region and a diode region. The transistor region includes an n-type first silicon carbide region having a first portion in contact with a first plane, a p-type second silicon carbide region, an n-type third silicon carbide region, a first electrode in contact with the first portion, the second silicon carbide region, and the third silicon carbide region, a second electrode in contact with a second plane, and a gate electrode. The diode region includes an n-type first silicon carbide region having a second portion in contact with the first plane, a p-type fourth silicon carbide region, a first electrode in contact with the second portion and the fourth silicon carbide region, and a second electrode. An occupied area per unit area of the fourth silicon carbide region is larger than an occupied area per unit area of the second silicon carbide region. The first diode region is provided between a first transistor region and a second transistor region.

Claims (32)

1. A semiconductor device comprising:

a plurality of transistor regions; and

at least one diode region,

wherein

the transistor regions include

a silicon carbide layer having a first plane and a second plane facing the first plane, the silicon carbide layer including an n-type first silicon carbide region having a plurality of first portions in contact with the first plane, a p-type second silicon carbide region provided between the first silicon carbide region and the first plane, and an n-type third silicon carbide region provided between the second silicon carbide region and the first plane,

a first electrode in contact with the first portions, the second silicon carbide region, and the third silicon carbide region,

a second electrode in contact with the second plane,

a gate electrode facing the second silicon carbide region, and

a gate insulating layer provided between the gate electrode and the second silicon carbide region,

the at least one diode region includes

the silicon carbide layer including the n-type first silicon carbide region having a plurality of second portions in contact with the first plane and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first plane,

the first electrode in contact with the second portions and the fourth silicon carbide region, and

the second electrode,

an occupied area per unit area of the fourth silicon carbide region projected onto the first plane is larger than an occupied area per unit area of the second silicon carbide region projected onto the first plane, and

a first diode region which is one of the at least one diode region is provided between a first transistor region which is one of the plurality of transistor regions and a second transistor region which is one of the plurality of transistor regions provided in a first direction parallel to the first plane with respect to the first transistor region.

2. The semiconductor device according to claim 1 , wherein a contact area per unit area between the first electrode and the fourth silicon carbide region is larger than a contact area per unit area between the first electrode and the second silicon carbide region.

3. The semiconductor device according to claim 1 , wherein a second distance between two second portions of the plurality of second portions adjacent to each other with the fourth silicon carbide region interposed therebetween is substantially equal to a first distance between two first portions of the plurality of first portions adjacent to each other with the second silicon carbide region interposed therebetween.

4. The semiconductor device according to claim 1 , wherein a second distance between two second portions adjacent to each other with the fourth silicon carbide region interposed therebetween is larger than a first distance between two first portions adjacent to each other with the second silicon carbide region interposed therebetween.

5. The semiconductor device according to claim 4 , wherein the second distance is equal to or less than two times the first distance.

6. The semiconductor device according to claim 1 , wherein the silicon carbide layer further includes a fifth silicon carbide region provided between the first silicon carbide region and the second silicon carbide region and has an n-type impurity concentration higher than an n-type impurity concentration of the first silicon carbide region, and a sixth silicon carbide region provided between the first silicon carbide region and the fourth silicon carbide region and has an n-type impurity concentration higher than an n-type impurity concentration of the first silicon carbide region.

7. The semiconductor device according to claim 6 , wherein the n-type impurity concentration of the sixth silicon carbide region is lower than the n-type impurity concentration of the fifth silicon carbide region.

8. The semiconductor device according to claim 1 , wherein a depth of the fourth silicon carbide region is greater than a depth of the second silicon carbide region.

9. The semiconductor device according to claim 1 , wherein a p-type impurity concentration of the fourth silicon carbide region is higher than a p-type impurity concentration of the second silicon carbide region.

10. The semiconductor device according to claim 1 , wherein the gate electrode extends in a second direction parallel to the first plane and orthogonal to the first direction.

11. The semiconductor device according to claim 1 , wherein the first transistor region is provided between a second diode region which is one of the at least one diode region and the first diode region.

12. The semiconductor device according to claim 1 , wherein a third diode region which is one of the at least one diode region is provided between the first transistor region and a third transistor region which is one of the plurality of transistor regions provided in a second direction parallel to the first plane and orthogonal to the first direction with respect to the first transistor region.

13. The semiconductor device according to claim 1 , wherein a width of the first diode region in the first direction is equal to or more than 30 μm.

14. An inverter circuit comprising the semiconductor device according to claim 1 .

15. A drive device comprising the semiconductor device according to claim 1 .

16. A vehicle comprising the semiconductor device according to claim 1 .

17. An elevator comprising the semiconductor device according to claim 1 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: OHASHI, TERUYUKI; KONO, HIROSHI; ASABA, SHUNSUKE; OGATA, TAKAHIRO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 060928/0676 →
Priority Claims (1)
JP 2021-190279 · Nov 24, 2021 · national
Continuity (1)
Related Publication 20230163166A1 · May 25, 2023
References Cited (15)
US 9246016B1 · Yen et al. · 2016 [cited by applicant]
US 9786778B1 · Morizuka · 2017 [cited by applicant]
US 20120286290A1 · Uchida · 2012 [cited by examiner]
US 20150372092A1 · Yamamoto · 2015 [cited by examiner]
US 20170250275A1 · Yen · 2017 [cited by examiner]
US 20200091925A1 · Lin · 2020 [cited by examiner]
US 20210074863A1 · Ohse et al. · 2021 [cited by applicant]
JP 2019169487 · 2019 [cited by applicant]
JP 20204956 · 2020 [cited by applicant]
JP 202013916A · 2020 [cited by applicant]
JP 202074426A · 2020 [cited by applicant]
JP 202144272 · 2021 [cited by applicant]
JP 2021145024 · 2021 [cited by applicant]
WO WO2019124378A1 · 2019 [cited by applicant]
Office Action mailed Feb. 18, 2025, in Japanese Application No. 2021-190279 filed Nov. 24, 20206/1 (w/computer-generated English translation). [cited by applicant]