IP Library Granted Patent US 9,484,414
Granted Patent B2
US 9,484,414 · App. 14/443,176 · Granted Nov 1, 2016

Semiconductor device

Inventors: Hirofumi Yamamoto (Osaka, JP); Toru Hiyoshi (Osaka, JP); Shinji Matsukawa (Itami, JP)
Assignee: Sumitomo Electric Industries, Ltd.
H01L29/1608H01L21/049H01L21/28H01L29/045H01L29/08H01L29/12H01L29/417H01L29/45H01L29/47H01L29/6606H01L29/66068H01L29/78H01L29/7802H01L29/7827H01L29/861H01L29/872H01L29/1075
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Quick Facts
Patent No.
US 9,484,414
App. No.
14/443,176
Granted
Nov 1, 2016
Kind
B2
Abstract

A MOSFET includes a silicon carbide substrate including a main surface having an off angle with respect to a {0001} plane and a source electrode formed in contact with the main surface. A base surface is exposed at at least a part of a contact interface of the silicon carbide substrate with the source electrode. With such a construction, the MOSFET achieves suppressed variation in threshold voltage.

Claims (17)

1. A semiconductor device, comprising:

a silicon carbide substrate including a main surface having an off angle with respect to a {0001} plane; and

an ohmic electrode formed in contact with said main surface,

a base surface being exposed at least a part of a contact interface of said silicon carbide substrate with said ohmic electrode, and

wherein a length of said base surface in a direction of the off angle is not smaller than 36 nm and not greater than 430 nm.

2. The semiconductor device according to claim 1 , wherein

said ohmic electrode contains at least one metal of Ni, Ti, and Al.

3. The semiconductor device according to claim 2 , wherein

said ohmic electrode is composed of a TiAlSi alloy or an NiSi alloy.

4. The semiconductor device according to claim 1 , further comprising:

an oxide film formed in contact with said silicon carbide substrate;

a gate electrode formed in contact with said oxide film such that said oxide film lies between the gate electrode and said silicon carbide substrate; and

a drain electrode formed in contact with said silicon carbide substrate, wherein

said ohmic electrode is a source electrode,

said source electrode and said drain electrode are configured such that a current which flows between said source electrode and said drain electrode can be controlled with a gate voltage applied to said gate electrode,

a difference between a first threshold voltage of said semiconductor device which is measured first and a second threshold voltage of said semiconductor device which is measured after application of stress to said semiconductor device continuously for 1000 hours is within ±0.2 V, and

application of said stress means application of said gate voltage of −15 V to said gate electrode while a voltage of said source electrode is 0 V and a voltage of said drain electrode is 0 V.

Assignments (2)
NUNC PRO TUNC ASSIGNMENT Recorded Jul 1, 2026
From: SUMITOMO ELECTRIC INDUSTRIES, LTD.
To: MITSUMI ELECTRIC CO., LTD.
Reel/Frame 075871/0320 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 15, 2015
From: YAMAMOTO, HIROFUMI; HIYOSHI, TORU; MATSUKAWA, SHINJI
To: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Reel/Frame 035648/0906 →
Priority Claims (1)
JP 2013-022221 · Feb 7, 2013 · national
Continuity (1)
Related Publication 20150372092A1 · Dec 24, 2015