Power amplifier device having dies with elongated bondpads connected through a device substrate
A power amplifier device includes first and second power transistor dies and a substrate. Each die includes an elongated bondpad and an integrated transistor with a terminal that is coupled to the elongated bondpad. The substrate is formed from a stack of multiple dielectric layers and multiple patterned conductive layers in an alternating arrangement, and a plurality of conductive vias electrically coupling portions of the conductive layers. The substrate includes elongated first and second die contacts exposed at a first substrate surface and connected to the first and second elongated bondpads, respectively. The substrate also includes a conductive structure connected between the first and second die contacts. The conductive structure is formed from portions of the patterned conductive layers and at least two vias of the plurality of conductive vias.
1 . A power amplifier device for a Doherty power amplifier that includes a first amplifier with a first output, a second amplifier with a second output, an impedance inverter/phase delay structure coupled between the first and second outputs of the first and second amplifiers, and a combining node, the power amplifier device comprising:
a first power transistor die with a first side and a second side that is perpendicular to the first side of the first power transistor die, wherein the first power transistor die includes
a first bondpad that is elongated and exposed at a first surface of the first power transistor die, wherein the first bondpad has a first bondpad length that is at least five times greater than a first bondpad width, and the first bondpad length is aligned in parallel with the first side of the first power transistor die, and
a first integrated transistor that includes a first terminal coupled to the first bondpad, wherein the first terminal corresponds to the first output of the first amplifier;
a second power transistor die with a first side and a second side that is perpendicular to the first side of the second power transistor die, wherein the second side of the second power transistor die faces the second side of the first power transistor die, and the second power transistor die includes
a second bondpad that is elongated and exposed at a first surface of the second power transistor die, wherein the second bondpad has a second bondpad length that is at least five times greater than a second bondpad width, and the second bondpad length is aligned in parallel with the first side of the second power transistor die, wherein the second bondpad is co-located with the combining node of the Doherty power amplifier, and
a second integrated transistor that includes a second terminal coupled to the second bondpad, wherein the second terminal corresponds to the second output of the second amplifier; and
a substrate formed from a stack of multiple dielectric layers and multiple patterned conductive layers in an alternating arrangement, and a plurality of conductive vias electrically coupling portions of the multiple patterned conductive layers, wherein the substrate includes
a first die contact that is exposed at a first substrate surface and that is elongated and connected to the first bondpad across the first bondpad length of the first bondpad,
a second die contact that is exposed at the first substrate surface and that is elongated and connected to the second bondpad across the second bondpad length of the second bondpad, and
a conductive structure aligned in parallel with the first and second bondpad lengths and connected between the first and second die contacts, wherein the conductive structure is formed from portions of the patterned conductive layers and at least two vias of the plurality of conductive vias, wherein the conductive structure corresponds to the impedance inverter/phase delay element of the Doherty power amplifier with a first end coupled to the first output of the first amplifier, and a second end coupled to the second output of the second amplifier and to the combining node.
2 . The power amplifier of claim 1 , wherein:
the first bondpad is an output bondpad for the first power transistor die, and the first terminal is a drain terminal of the first integrated transistor; and
the second bondpad is an output bondpad for the second power transistor die, and the second terminal is a drain terminal of the second integrated transistor.
3 . The power amplifier device of claim 1 , wherein the first die contact and the first bondpad are connected together using solder, sintering, or brazing.
4 . The power amplifier device of claim 1 , wherein the conductive structure comprises:
a first conductive trace formed from a portion of a first patterned conductive layer of the patterned conductive layers and extending between the first and second power transistor dies;
a first via of the plurality of conductive vias connected between the first die contact and the first conductive trace; and
a second via of the plurality of conductive vias connected between the second die contact and the first conductive trace.
5 . The power amplifier device of claim 4 , wherein:
the first via is a first trench via that is elongated; and
the second via is a second trench via that is elongated.
6 . The power amplifier device of claim 4 , wherein the conductive structure further comprises:
a second conductive trace formed from a portion of a second patterned conductive layer of the patterned conductive layers; and
one or more additional vias connected between the first conductive trace and the second conductive trace.
7 . The power amplifier device of claim 6 , wherein:
each of the one or more additional vias is a trench via.
8 . The power amplifier device of claim 6 , wherein the conductive structure further comprises:
a third conductive trace formed from a portion of a third patterned conductive layer of the patterned conductive layers; and
one or more further additional vias connected between the first conductive trace and the third conductive trace.
9 . The power amplifier device of claim 1 , wherein:
the first power transistor die further includes
a third bondpad that is exposed at the first surface of the first power transistor die, wherein the third bondpad is coupled to a second terminal of the first integrated transistor,
a first conductive layer at a second surface of the first power transistor die, wherein the first conductive layer is coupled to a third terminal of the first integrated transistor;
the second power transistor die further includes
a fourth bondpad that is exposed at the first surface of the second power transistor die, wherein the fourth bondpad is coupled to a second terminal of the second integrated transistor, and
a second conductive layer at a second surface of the second power transistor die, wherein the second conductive layer is coupled to a third terminal of the second integrated transistor; and
the substrate further includes
a third die contact that is exposed at the first substrate surface and that is connected to the third bondpad, and
a fourth die contact that is exposed at the first substrate surface and that is connected to the fourth bondpad.
10 . The power amplifier device of claim 9 , wherein:
the third bondpad and the third die contact are elongated;
a second terminal of the first integrated transistor is coupled to the third bondpad;
the fourth bondpad and the fourth die contact are elongated; and
a second terminal of the second integrated transistor is coupled to the fourth bondpad; and
the substrate further includes
a first patterned conductor formed from a portion of a first patterned conductive layer and having a first edge that is elongated and that overlies the third bondpad;
a first via of the plurality of conductive vias connected between the third bondpad and the first patterned conductor;
a second patterned conductor formed from a portion of the first patterned conductive layer and having a second edge that is elongated and that overlies the fourth bondpad; and
a second via of the plurality of conductive vias connected between the fourth bondpad and the second patterned conductor.
11 . The power amplifier device of claim 9 , wherein:
the first terminal of the first integrated transistor is a first drain terminal;
the second terminal of the first integrated transistor is a first gate terminal;
the third terminal of the first integrated transistor is a first source terminal;
the first terminal of the second integrated transistor is a second drain terminal;
the second terminal of the second integrated transistor is a second gate terminal; and
the third terminal of the second integrated transistor is a second source terminal.
12 . The power amplifier device of claim 1 , further comprising:
a plurality of additional contacts exposed at a second substrate surface;
one or more surface-mount components connected to the plurality of additional components at the second substrate surface, wherein the one or more surface-mount components are electrically coupled through the patterned conductive layers and the conductive vias to the first and second die contacts; and
an encapsulation material layer covering the one or more surface-mount components and the second substrate surface, wherein the encapsulation material layer defines a surface of the power amplifier device.
13 . The power amplifier device of claim 12 , wherein the one or more surface mount components form portions of amplifier circuitry selected from pre-amplifier transistors, power splitting circuitry, harmonic termination circuitry, inductors, capacitors, and impedance matching circuitry.
14 . The power amplifier device of claim 1 , wherein the substrate further comprises:
first and second interconnect contacts exposed at the first substrate surface;
a first conductive interconnect connected to the first interconnect contact and electrically coupled to the multiple patterned conductive layers and to a control terminal of the first integrated transistor; and
a second conductive interconnect connected to the second interconnect contact and electrically coupled to the multiple patterned conductive layers and to a drain terminal of the second integrated transistor.
15 . The power amplifier device of claim 1 , wherein the substrate further comprises:
first and second interconnect contacts exposed at a second substrate surface;
a first conductive interconnect connected to the first interconnect contact and electrically coupled to the multiple patterned conductive layers and to a control terminal of the first integrated transistor; and
a second conductive interconnect connected to the second interconnect contact and electrically coupled to the multiple patterned conductive layers and to a drain terminal of the second integrated transistor.
16 . The power amplifier device of claim 1 , further comprising:
one or more thermal structures contacting second surfaces of the first and second power transistor dies.
17 . The power amplifier device of claim 1 , wherein the first and second power transistor dies comprise a carrier amplifier die and a peaking amplifier die of the Doherty power amplifier.
18 . An amplifier system comprising:
a system substrate; and
a power amplifier device coupled to the system substrate, wherein the power amplifier device forms a portion of a Doherty power amplifier that includes a first amplifier with a first output, a second amplifier with a second output, an impedance inverter/phase delay structure coupled between the first and second outputs of the first and second amplifiers, and a combining node, and wherein the power amplifier device includes
a first power transistor die with a first side and a second side that is perpendicular to the first side of the first power transistor die, wherein the first power transistor die includes
a first bondpad that is elongated and exposed at a first surface of the first power transistor die, wherein the first bondpad has a first bondpad length that is at least five times greater than a first bondpad width, and the first bondpad length is aligned in parallel with the first side of the first power transistor die, and
a first integrated transistor that includes a first terminal coupled to the first bondpad, wherein the first terminal corresponds to the first output of the first amplifier,
a second power transistor die with a first side and a second side that is perpendicular to the first side of the second power transistor die, wherein the second side of the second power transistor die faces the second side of the first power transistor die, and the second power transistor die includes
a second bondpad that is elongated and exposed at a first surface of the second power transistor die, wherein the second bondpad has a second bondpad length that is at least five times greater than a second bondpad width, and the second bondpad length is aligned in parallel with the first side of the second power transistor die, wherein the second bondpad is co-located with the combining node of the Doherty power amplifier, and
a second integrated transistor that includes a second terminal coupled to the second bondpad, wherein the second terminal corresponds to the second output of the second amplifier, and
a device substrate formed from a stack of multiple dielectric layers and multiple patterned conductive layers in an alternating arrangement, and a plurality of conductive vias electrically coupling portions of the multiple patterned conductive layers, wherein the device substrate includes
a first die contact that is exposed at a first substrate surface and that is elongated and connected to the first bondpad across the first bondpad length of the first bondpad,
a second die contact that is exposed at the first substrate surface and that is elongated and connected to the second bondpad across the second bondpad length of the second bondpad, and
a conductive structure aligned in parallel with the first and second bondpad lengths and connected between the first and second die contacts, wherein the conductive structure is formed from portions of the patterned conductive layers and at least two vias of the plurality of conductive vias, wherein the conductive structure corresponds to the impedance inverter/phase delay element of the Doherty power amplifier with a first end coupled to the first output of the first amplifier, and a second end coupled to the second output of the second amplifier and to the combining node.
19 . The amplifier system of claim 18 , wherein:
the system substrate includes a heat extraction component; and
the power amplifier device further includes one or more thermal structures contacting second surfaces of the first and second power transistor dies and connected to the heat extraction component of the system substrate.
20 . The power amplifier device of claim 1 , wherein the substrate further comprises:
an output conductor formed from a portion of one of the multiple patterned conductive layers, wherein an end of the output conductor is connected to and aligned over the second die contact.
21 . The power amplifier device of claim 1 , wherein the conductive structure extends over and between the second sides of the first and second power transistor dies.