Flexible partitioning of GPU resources
Described herein is a partitionable graphics processor having a plurality of flexibly partitioned processing resources. One embodiment provides a graphics processor comprising a plurality of processing resources configurable to be flexibly partitioned into a plurality of resource partitions and circuitry to compose multiple graphics processor device partitions from the plurality of resource partitions. The multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units.
1 . A graphics processor comprising:
a plurality of processing resources configurable to be flexibly partitioned into a plurality of resource partitions, the plurality of processing resources respectively including a vector engine and a matrix engine; and
circuitry to compose multiple graphics processor device partitions from the plurality of resource partitions, wherein the multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units, the circuitry is configurable to compose a first partition and a second partition, the first partition includes a first processing resource, and the second partition includes a second processing resource.
2 . The graphics processor as in claim 1 , wherein the circuitry includes a network on chip interconnect that is configurable to compose a virtual graphics core including selected processing resources.
3 . The graphics processor as in claim 2 , wherein the circuitry is configured to compose a first virtual graphics core including the first processing resource for the first partition and a second virtual graphics core including the second processing resource for the second partition.
4 . The graphics processor as in claim 3 , wherein the circuitry is configured to map the matrix engine of the second processing resource to the first partition and map the vector engine of the second processing resource to the second partition.
5 . The graphics processor as in claim 4 , wherein the first partition is configured to execute a matrix instruction via the matrix engine of the first processing resource and the matrix engine of the second processing resource.
6 . The graphics processor as in claim 4 , wherein the first partition is configured to execute a first matrix instruction via the matrix engine of the first processing resource and a second matrix instruction via the matrix engine of the second processing resource.
7 . The graphics processor as in claim 4 , wherein the first processing resource and the second processing resource each include a media engine and a ray tracing unit, the circuitry is configured to map the media engine of the first processing resource and the media engine of the second processing resource to the second partition and map the ray tracing unit of the first processing resource and the second processing resource to the first partition.
8 . The graphics processor as in claim 4 , further comprising a system interface to present the graphics processor to a host system.
9 . The graphics processor as in claim 8 , wherein the system interface is configured to present the multiple graphics processor device partitions as separate sub-devices of the graphics processor.
10 . The graphics processor as in claim 9 , the separate sub-devices to be presented as single-root input/output virtualization virtual functions or scalable input/output virtualization virtual devices.
11 . A data processing system comprising:
a system interface; and
a graphics processor coupled with the system interface, the graphics processor including:
a plurality of processing resources configurable to be flexibly partitioned into a plurality of resource partitions, the plurality of processing resources respectively including a vector engine and a matrix engine; and
circuitry to compose multiple graphics processor device partitions from the plurality of resource partitions, wherein the multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units and presented via the system interface as multiple sub-devices of the graphics processor, the circuitry is configurable to compose a first partition and a second partition, the first partition includes a first processing resource, and the second partition includes a second processing resource.
12 . The data processing system as in claim 11 , wherein the circuitry includes a network on chip interconnect that is configurable to compose a virtual graphics core including selected processing resources.
13 . The data processing system as in claim 12 , wherein the circuitry is configured to compose a first virtual graphics core including the first processing resource for the first partition and a second virtual graphics core including the second processing resource for the second partition.
14 . The data processing system as in claim 13 , wherein the circuitry is configured to map the matrix engine of the second processing resource to the first partition and map the vector engine of the second processing resource to the second partition.
15 . The data processing system as in claim 14 , wherein the first partition is configured to execute a matrix instruction via the matrix engine of the first processing resource and the matrix engine of the second processing resource.
16 . The data processing system as in claim 14 , wherein the first partition is configured to execute a first matrix instruction via the matrix engine of the first processing resource and a second matrix instruction via the matrix engine of the second processing resource.
17 . A method comprising:
configuring a number of compute partitions for a graphics processor, the graphics processor including a processing resource having a plurality of vector engines and a plurality of matrix engines, wherein the processing resource is asymmetrically partitionable into a plurality of compute partitions;
composing a plurality of device partitions of the graphics processor via selection of one or more of the plurality of compute partitions for each device partition, the plurality of device partitions including a first device partition and a second device partition, wherein the first device partition includes the plurality of matrix engines and a first portion of the plurality of vector engines, and the second device partition includes a second portion of the plurality of vector engines; and
presenting the first device partition as a first sub-device and the second device partition as a second sub-device.
18 . The method as in claim 17 , wherein the graphics processor is included in a multi-client server device and the method further comprises presenting the first sub-device to a first client of the server device and presenting the second sub-device to a second client of the server device.
19 . The method as in claim 17 , further comprising configuring a number of cache and memory partitions for the graphics processor, wherein composing the plurality of device partitions of the graphics processor includes selecting one or more of a plurality of cache and memory partitions for each device partition.
20 . The method as in claim 17 , further comprising configuring a memory bandwidth allocation for each device partition, wherein configuring a memory bandwidth allocation for each device partition includes automatically determining an increased memory bandwidth allocation for the first device partition based on inclusion of the plurality of matrix engines in the first device partition.