Wafer level sequencing flow cell fabrication
A method for forming sequencing flow cells can include providing a semiconductor wafer covered with a dielectric layer and forming a patterned layer on the dielectric layer. The patterned layer has a differential surface that includes alternating first surface regions and second surface regions. The method can also include attaching a cover wafer to the semiconductor wafer to form a composite wafer structure including a plurality of flow cells. The composite wafer structure can then be singulated to form a plurality of dies. Each die forms a sequencing flow cell. The sequencing flow cell can include a flow channel between a portion of the patterned layer and a portion of the cover wafer, an inlet, and an outlet. Further, the method can include functionalizing the sequencing flow cell to create differential surfaces.
1. A method for forming sequencing flow cells, comprising:
providing a semiconductor wafer covered with a dielectric layer;
forming a patterned layer on the dielectric layer, the patterned layer having differential surface regions that include alternating first surface regions and second surface regions;
forming a first covering layer selectively on the first surface regions by exposing the patterned layer to a first material;
form a second covering layer selectively on the second surface regions and not on the first surface regions, by exposing the patterned layer to a second material;
wherein the method further comprises selecting the first material and the second material to adjust hydrophobicity of the first covering layer and the second covering layer;
attaching a cover wafer to the semiconductor wafer to form a composite wafer structure that includes a plurality of sequencing flow cells, wherein each sequencing flow cell includes:
a flow channel between the patterned layer and the cover wafer;
one or more first surface regions in the patterned layer;
one or more second surface regions in the patterned layer; and
an inlet and an outlet coupled to the flow channel; and
singulating the composite wafer structure to form a plurality of dies, each die including a sequencing flow cell.
2. The method of claim 1 , wherein one of the first covering layer and the second covering layer is hydrophobic, and the other one of the first covering layer and the second covering layer is hydrophilic.
3. The method of claim 2 , further comprising forming a plurality of through holes in the semiconductor wafer before attaching the cover wafer, the plurality of through holes configured as inlets and outlets for the plurality of sequencing flow cells.
4. The method of claim 2 , further comprising forming inlets and outlets in the cover wafer before attaching the cover wafer to the semiconductor wafer.
5. The method of claim 1 , wherein forming the first covering layer comprises exposing a metal oxide region to polyvinylphosphonic acid (PVPA) to form a hydrophilic covering layer.
6. The method of claim 1 , wherein forming the first covering layer comprises exposing a metal oxide region to 12-Hydroxy dodecyl phosphate, (OH-DDPO4) in a SAM (self assembled monolayer) to form a hydrophilic covering layer.
7. The method of claim 1 , wherein forming the first covering layer comprises exposing a metal oxide region to ammonium salt of hydroxy dodecyl phosphate to form a hydrophobic covering layer.
8. The method of claim 1 , wherein forming the second covering layer comprises exposing a silicon oxide region to a hydrophobic silane to form a hydrophobic covering layer.
9. The method of claim 8 , wherein the hydrophobic silane comprises fluorinated Alkyl-Silanes or dialkyl-Silanes.
10. The method of claim 1 , wherein forming the second covering layer comprises exposing a silicon oxide region to a hydrophilic silane to form a hydrophilic covering layer.
11. The method of claim 10 , wherein the hydrophilic silane comprises Hydroxyakyl terminated silane.
12. A method for forming sequencing flow cells, comprising:
providing a semiconductor substrate covered with a dielectric layer;
forming a patterned layer on the dielectric layer, the patterned layer having differential surface regions that include alternating first surface regions and second surface regions;
forming a first covering layer selectively on the first surface regions by exposing the patterned layer to a first material;
form a second covering layer selectively on the second surface regions and not on the first surface regions, by exposing the patterned layer to a second material, wherein one of the first covering layer and the second covering layer is hydrophobic, and the other one of the first covering layer and the second covering layer is hydrophilic; and
attaching a cover substrate to the semiconductor substrate to form a composite wafer structure that includes a plurality of sequencing flow cells, wherein each sequencing flow cell includes:
a flow channel between the patterned layer and the cover substrate;
one or more first surface regions in the patterned layer;
one or more second surface regions in the patterned layer; and
an inlet and an outlet coupled to the flow channel.
13. The method of claim 12 , further comprising forming a plurality of through holes in the semiconductor substrate before attaching the cover substrate, the plurality of through holes configured as inlets and outlets for the plurality of sequencing flow cells.
14. The method of claim 12 , further comprising forming inlets and outlets in the cover substrate before attaching the cover substrate to the semiconductor substrate.
15. The method of claim 12 , wherein forming the first covering layer comprises exposing a metal oxide region to polyvinylphosphonic acid (PVPA) to form a hydrophilic covering layer.
16. The method of claim 12 , wherein forming the first covering layer comprises exposing a metal oxide region to 12-Hydroxy dodecyl phosphate, (OH-DDPO4) in a SAM (self assembled monolayer) to form a hydrophilic covering layer.
17. The method of claim 12 , wherein forming the first covering layer comprises exposing a metal oxide region to ammonium salt of hydroxy dodecyl phosphate to form a hydrophobic covering layer.
18. The method of claim 12 , wherein forming the second covering layer comprises exposing a silicon oxide region to a hydrophobic silane to form a hydrophobic covering layer, wherein the hydrophobic silane comprises fluorinated Alkyl-Silanes or dialkyl-Silanes.
19. The method of claim 12 , wherein forming the second covering layer comprises exposing a silicon oxide region to a hydrophilic silane to form a hydrophilic covering layer, wherein the hydrophilic silane comprises Hydroxyakyl terminated silane.
20. The method of claim 12 , wherein the semiconductor substrate is a semiconductor wafer, and the method further comprising singulating the composite wafer structure to form a plurality of dies, each die including a sequencing flow cell.
21. A method for forming sequencing flow cells, comprising:
on a semiconductor substrate including a patterned layer on a surface of the semiconductor substrate, the patterned layer having differential surface regions that include alternating first surface regions and second surface regions, forming a first covering layer selectively on the first surface regions by exposing the patterned layer to a first material; and
attaching a cover substrate to the semiconductor substrate to form a composite wafer structure that includes a plurality of sequencing flow cells, wherein each sequencing flow cell includes:
a flow channel between the patterned layer and the cover substrate;
one or more first surface regions in the patterned layer;
one or more second surface regions in the patterned layer; and
an inlet and an outlet coupled to the flow channel;
further comprising forming a plurality of through holes in the semiconductor substrate before attaching the cover substrate, the plurality of through holes configured as inlets and outlets for the plurality of sequencing flow cells.
22. The method of claim 21 , further comprising forming a second covering layer selectively on the second surface regions and not on the first surface regions, by exposing the patterned layer to a second material, wherein one of the first covering layer and the second covering layer is hydrophobic, and the other one of the first covering layer and the second covering layer is hydrophilic.
23. The method of claim 22 , wherein forming the first covering layer comprises exposing a metal oxide region to polyvinylphosphonic acid (PVPA) to form a hydrophilic covering layer.
24. The method of claim 22 , wherein forming the first covering layer comprises exposing a metal oxide region to 12-Hydroxy dodecyl phosphate, (OH-DDPO4) in a SAM (self assembled monolayer) to form a hydrophilic covering layer.
25. The method of claim 22 , wherein forming a second covering layer comprises exposing a silicon oxide region to a hydrophobic silane to form a hydrophobic covering layer, wherein the hydrophobic silane comprises fluorinated Alkyl-Silanes or dialkyl-Silanes.
26. The method of claim 22 , wherein forming the second covering layer comprises exposing a silicon oxide region to a hydrophilic silane to form a hydrophilic covering layer, wherein the hydrophilic silane comprises Hydroxyakyl terminated silane.
27. The method of claim 22 , wherein the semiconductor substrate is a semiconductor wafer, and the method further comprising singulating the composite wafer structure to form a plurality of dies, each die including a sequencing flow cell.