Conformal titanium nitride-based thin films and methods of forming same
The disclosed technology generally relates to forming a titanium nitride-based thin films, and more particularly to a conformal and smooth titanium nitride-based thin films and methods of forming the same. In one aspect, a method of forming a thin film comprising one or both of TiSiN or TiAlN comprises exposing a semiconductor substrate to one or more vapor deposition cycles at a pressure in a reaction chamber greater than 1 torr, wherein a plurality of the vapor deposition cycles comprises an exposure to a titanium (Ti) precursor, an exposure to a nitrogen (N) precursor and an exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.
1. A method of forming a thin film, the method comprising:
forming a thin film comprising one or both of TiSiN and TiAIN by exposing a semiconductor substrate to a plurality of vapor deposition cycles at a pressure in a reaction chamber greater than 5 torr, wherein the vapor deposition cycles comprise exposures to a titanium (Ti) precursor, exposures to a nitrogen (N) precursor and exposures to one or both of a silicon (Si) precursor and an aluminum (Al) precursor,
wherein forming the thin film comprises exposing the semiconductor substrate to the plurality of vapor deposition cycles without an aid of a plasma.
2. The method of claim 1 , wherein the pressure in the reaction chamber is less than 10 torr.
3. The method of claim 1 , wherein, prior to forming the thin film, the semiconductor substrate is patterned to have a surface topography such that a ratio of an entire front surface area of the semiconductor substrate to an entire front surface area of an unpatterned flat semiconductor substrate having the same substrate diameter as the semiconductor substrate exceeds 2.
4. The method of claim 3 , wherein the semiconductor substrate comprises a plurality of trenches or vias formed thereon, wherein the trenches or vias comprise a dielectric sidewall surface and an aspect ratio exceeding 5.
5. The method of claim 1 , wherein exposing the semiconductor substrate to the plurality of vapor deposition cycles comprises:
exposing the semiconductor substrate to a plurality of first deposition phases, wherein the first deposition phases comprise the exposure to the Ti precursor and the exposure to the N precursor; and
exposing the semiconductor substrate to a plurality of second deposition phases, wherein the second deposition phases comprise the exposure to one or both of the Si precursor and the Al precursor.
6. The method of claim 5 , wherein the second deposition phases further comprise a further exposure to the N precursor.
7. The method of claim 5 , wherein a ratio of a number of the first deposition phases to a number of the second deposition phases is such that the thin film is at least partially amorphous.
8. The method of claim 7 , wherein the ratio of the number of the first deposition phases to the number of the second deposition phases is equal to or less than 15:1.
9. The method of claim 5 , wherein a number of the first deposition phases and a number of the second deposition phases are such that the thin film is substantially homogenous in a layer depth direction.
10. The method of claim 9 , wherein the number of the first deposition phases and the number of the second deposition phases do not exceed about 50 cycles.
11. The method of claim 1 , wherein the thin film comprises TiSiN, and wherein the Si precursor is a compound selected from the group consisting of SiH 4 , Si 2 H 6 , SiH 2 Cl 2 , SiH 3 Cl, Si 2 Cl 6 and Si 3 Cl 8 .
12. The method of claim 1 , wherein the thin film comprises TiAIN, and wherein the Al precursor is a compound selected from the group consisting of tri-methyl aluminum, tri-iso-butyl-aluminum and tris (dimethylamido) aluminum.
13. The method of claim 1 , wherein exposing the semiconductor substrate to the vapor deposition cycles is performed at a substrate temperature of 450° C. to 650° C.
14. A method of forming a diffusion barrier, comprising:
providing a semiconductor substrate comprising a plurality of openings formed thereon; and
lining surfaces of the openings with a diffusion barrier layer comprising one or both of TiSiN and TiAIN by a thermal cyclic vapor deposition process without an aid of a plasma, comprising exposing the semiconductor substrate to a plurality of vapor deposition cycles at a pressure in a reaction chamber greater than 5 torr, wherein the vapor deposition cycles comprise exposures to a titanium (Ti) precursor, exposures to a nitrogen (N) precursor and exposures to one or both of a silicon (Si) precursor and an aluminum (Al) precursor.
15. The method of claim 14 , wherein each of the openings comprises a dielectric sidewall and an aspect ratio exceeding 5.
16. The method of claim 14 , wherein lining the surfaces of the openings comprises conformally lining the surfaces such that a ratio of thicknesses of the diffusion barrier layer formed on lower 25% of a height of the openings and upper 25% of the height of the openings exceeds 0.6.
17. The method of claim 14 , wherein exposing the semiconductor substrate to the vapor deposition cycles comprises:
exposing the semiconductor substrate to a plurality of first deposition phases, wherein the first deposition phases comprise the exposures to the Ti precursor and the exposures to the N precursor; and
exposing the semiconductor substrate to a plurality of second deposition phases, wherein the second deposition phases comprise the exposures to one or both of the Si precursor and the Al precursor.
18. The method of claim 17 , wherein the second deposition phases further comprise a further exposure to the N precursor.
19. The method of claim 17 , wherein a ratio of a number of the first deposition phases to a number of the second deposition phases is such that the diffusion barrier is at least partially amorphous.