Gate structures for semiconductor devices
A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes first and second pair of source/drain regions disposed on a substrate, first and second nanostructured channel regions, and first and second gate structures with effective work function values different from each other. The first and second gate structures include first and second high-K gate dielectric layers, first and second barrier metal layers with thicknesses different from each, first and second work function metal (WFM) oxide layers with thicknesses substantially equal to each other disposed on the first and second barrier metal layers, respectively, a first dipole layer disposed between the first WFM oxide layer and the first barrier metal layer, and a second dipole layer disposed between the second WFM oxide layer and the second barrier metal layer.
1. A method, comprising:
forming first and second fin structures on a substrate;
forming a high-K gate dielectric layer on the first and second fin structures;
forming first and second metal layers of different thicknesses on first and second portions of the high-K gate dielectric layer;
forming first and second metal oxide layers of substantially equal thicknesses on the first and second metal layers, respectively;
forming a first dipole layer between the first metal oxide layer and the first metal layer;
forming a second dipole layer between the second metal oxide layer and the second metal layer; and
forming first and second gate metal fill layers on the first and second metal oxide layers, respectively.
2. The method of claim 1 , wherein forming the first and second dipole layers comprises performing a drive-in anneal process on the first and second metal oxide layers.
3. The method of claim 1 , wherein forming the first and second dipole layers comprises performing first and second drive-in anneal processes at temperatures different from each other on the first and second metal oxide layers.
4. The method of claim 1 , wherein forming the first and second dipole layers comprises performing a soak anneal process and a spike anneal process at temperatures different from each other on the first and second metal oxide layers.
5. The method of claim 1 , further comprising oxidizing top surfaces of the first and second metal layers to form third and fourth metal oxide layers during the forming of the first metal oxide layer.
6. The method of claim 1 , wherein forming the first metal oxide layer comprises forming a rare-earth metal oxide layer.
7. The method of claim 1 , wherein forming the second metal oxide layer comprises forming an aluminum-based oxide layer.
8. The method of claim 1 , wherein forming the first and second metal layers comprises:
forming a first stack of nitride layers on the first portion of the high-K gate dielectric layer; and
forming a second stack of nitride layers on the second portion of the high-K gate dielectric layer, wherein the first stack of nitride layers is thicker than the second stack of nitride layers.
9. The method of claim 1 , wherein forming the first and second metal layers comprises:
depositing a first nitride layer comprising first and second layer portions on the first and second portions of the high-K gate dielectric layer, respectively;
etching the first layer portion to expose the first portion of the high-K gate dielectric layer; and
depositing a second nitride layer on the first portion of the high-K gate dielectric layer and on the second layer portion.
10. The method of claim 1 , wherein forming the first metal oxide layer comprises:
depositing a rare-earth metal oxide layer comprising first and second layer portions on the first and second metal layers, respectively; and
etching the second layer portion to expose the second metal layer.
11. The method of claim 1 , wherein forming the second metal oxide layer comprises:
depositing an aluminum-based oxide layer comprising first and second layer portions on the first metal oxide layer and on the second metal layer; and
etching the first layer portion to expose the first metal oxide layer.
12. A method, comprising:
forming first and second nanostructured channel regions on a substrate;
forming a high-K gate dielectric layer surrounding the first and second nanostructured channel regions;
forming first and second metal layers of different thicknesses on first and second portions of the high-K gate dielectric layer;
forming first and second metal oxide layers of substantially equal thicknesses on the first and second metal layers, respectively;
performing first and second drive-in anneal processes at temperatures different from each other on the first and second metal oxide layers; and
forming first and second gate metal fill layers on the first and second metal oxide layers, respectively.
13. The method of claim 12 , wherein forming the first metal oxide layer comprises forming a rare-earth metal (REM) oxide layer with an REM concentration profile having a peak REM concentration at an interface between the first metal oxide layer and the first metal layer.
14. The method of claim 12 , wherein forming the second metal oxide layer comprises forming an aluminum (A 1 )-based oxide layer with an Al concentration profile having a peak Al concentration at an interface between the second metal oxide layer and the second metal layer.
15. The method of claim 12 , further comprising depositing third and fourth metal layers on the first and second metal oxide layers.
16. The method of claim 12 , wherein forming the first and second metal layers comprises:
forming a first nitride layer with a first thickness on the first portion of the high-K gate dielectric layer; and
forming a second nitride layer with a second thickness on the second portion of the high-K gate dielectric layer, wherein the first and second thicknesses are different from each other.
17. A semiconductor device, comprising:
a substrate;
first and second fin structures disposed on the substrate; and
first and second gate structures disposed on the first and second fin structures, respectively, comprising:
first and second metal layers with thicknesses different from each other disposed on the first and second high-K gate dielectric layers, respectively;
first and second metal oxide layers with thicknesses substantially equal to each other disposed on the first and second metal layers, respectively;
a first dipole layer disposed between the first metal oxide layer and the first metal layer; and
a second dipole layer disposed between the second metal oxide layer and the second metal layer.
18. The semiconductor device of claim 17 , wherein the first and second gate structures further comprise third and fourth metal oxide layers disposed on the first and second metal layers, respectively; and
wherein the third and fourth barrier metal oxide layers comprise an oxide of a metal in the first and second metal layers, respectively.
19. The semiconductor device of claim 17 , wherein the first and second dipole layers comprise metal ions of rare-earth metals or of metals from group IIA, IIIB, or IVB of the periodic table.
20. The semiconductor device of claim 17 , wherein the first and second dipole layers comprise metal ions of aluminum-based metals or of metals from group IHA, VA, or VB of the periodic table.