Sidewall spacer structure to increase switching performance of ferroelectric memory device

1. A method for forming an integrated chip, the method comprising:

forming a first conductive structure over a substrate;

forming a ferroelectric layer over the first conductive structure;

forming a sidewall spacer structure along sidewalls of the ferroelectric layer; and

forming a second conductive structure over the ferroelectric layer and the sidewall spacer structure, wherein outer opposing sidewalls of the second conductive structure are aligned with outer opposing sidewalls of the sidewall spacer structure.

2. The method of claim 1 , wherein forming the sidewall spacer structure comprises:

forming a blocking layer over the first conductive structure;

depositing the sidewall spacer structure with the blocking layer in place, wherein the blocking layer is configured to block deposition of the sidewall spacer structure on an upper surface of the blocking layer; and

removing the blocking layer.

3. The method of claim 1 , further comprising:

forming a dielectric structure over the substrate and around the first conductive structure, wherein the dielectric structure comprises sidewalls defining an opening over the first conductive structure; and

wherein forming the sidewall spacer structure comprises depositing the sidewall spacer structure along the sidewalls of the dielectric structure and a top surface of the dielectric structure and performing a planarization process into the sidewall spacer structure.

4. The method of claim 3 , wherein the sidewall spacer structure is deposited by chemical vapor deposition or atomic layer deposition.

5. The method of claim 1 , wherein a bottom surface of the sidewall spacer structure abuts or is above a top surface of the first conductive structure.

6. The method of claim 1 , wherein the ferroelectric layer has a first width and the sidewall spacer structure has a second width, wherein a ratio of the first width to the second width is within a range of about 5:1 to about 30:1.

7. The method of claim 1 , further comprising:

forming a gate dielectric layer between the first conductive structure and the substrate; and

forming a pair of source/drain regions within the substrate and on opposing sides of the ferroelectric layer, wherein the pair of source/drain regions is formed after forming the sidewall spacer structure.

8. The method of claim 1 , wherein a dielectric constant of the ferroelectric layer is greater than a dielectric constant of the sidewall spacer structure.

9. The method of claim 1 , wherein the second conductive structure contacts a top surface of the ferroelectric layer and a top surface of the sidewall spacer structure.

10. The method of claim 1 , wherein a height of the sidewall spacer structure is less than a height of the ferroelectric layer.

11. A method for forming an integrated chip, the method comprising:

forming a first conductive structure over a substrate;

forming a ferroelectric layer over the first conductive structure, wherein the ferroelectric layer comprises a first dielectric material; and

forming a sidewall spacer structure over the first conductive structure, wherein the sidewall spacer structure laterally encloses the ferroelectric layer, wherein the sidewall spacer structure comprises a second dielectric material different from the first dielectric material, wherein a dielectric constant of the second dielectric material is less than a dielectric constant of the first dielectric material, and wherein the sidewall spacer structure is formed before forming the ferroelectric layer over the first conductive structure.

12. The method of claim 11 , wherein outer sidewalls of the ferroelectric layer are aligned with outer sidewalls of the sidewall spacer structure.

13. The method of claim 11 , further comprising:

performing a planarization process on the sidewall spacer structure and the ferroelectric layer, wherein a top surface of the sidewall spacer structure is co-planar with a top surface of the ferroelectric layer.

14. The method of claim 11 , further comprising:

forming a gate dielectric layer between the substrate and the ferroelectric layer, wherein outer sidewalls of the ferroelectric layer are spaced between or aligned with outer sidewalls of the gate dielectric layer.

15. The method of claim 11 , further comprising:

forming a second conductive structure over the ferroelectric layer, wherein the sidewall spacer structure is formed before forming the second conductive structure.

16. The method of claim 11 , further comprising:

forming a dielectric structure over the substrate and around the sidewall spacer structure, wherein a dielectric constant of the dielectric structure is less than the dielectric constant of the second dielectric material.

17. A method for forming a ferroelectric memory device, the method comprising:

forming a first conductive structure over a substrate;

forming a dielectric structure over the substrate such that the dielectric structure comprises sidewalls defining an opening that exposes an upper surface of the first conductive structure;

selectively depositing a self-assembled monolayer (SAM) along the upper surface of the first conductive structure;

selectively depositing a sidewall spacer layer along the sidewalls of the dielectric structure and an upper surface of the dielectric structure, wherein the SAM is configured to block deposition of the sidewall spacer layer along an upper surface of the SAM;

performing a removal process to remove the SAM from the upper surface of the first conductive structure;

depositing a ferroelectric film over the first conductive structure and the sidewall spacer layer;

performing a planarization process into the ferroelectric film and the sidewall spacer layer, thereby forming a ferroelectric layer and a sidewall spacer structure, respectively; and

forming a second conductive structure over the ferroelectric layer and the sidewall spacer structure.

18. The method of claim 17 , further comprising:

forming a gate dielectric layer over the substrate such that the gate dielectric layer underlies the first conductive structure; and

forming a gate electrode between the gate dielectric layer and the first conductive structure such that sidewalls of the gate electrode and sidewalls of the sidewall spacer structure are aligned.

19. The method of claim 17 , wherein the sidewall spacer layer is deposited by chemical vapor deposition or atomic layer deposition.

20. The method of claim 17 , wherein the ferroelectric layer comprises a first metal oxide and the sidewall spacer structure comprises a second metal oxide different from the first metal oxide.