Interconnect structure having different dimensions for connected circuit blocks in integrated circuit
A interconnect structure for an integrated circuit may include: a metal line including a plurality of sections having different thicknesses along a 1 st direction; and a plurality of vias respectively protruding from the plurality of sections of the metal line.
1 . An interconnect structure for an integrated circuit, the interconnect structure comprising:
a metal line extending in a 1 st direction perpendicular to a 2 nd direction, the metal line comprising a plurality of sections having different thicknesses in a 3 rd direction perpendicular to the 1 st direction and the 2 nd direction; and
a plurality of vias respectively protruding from the sections of the metal line in the 3 rd direction,
wherein the metal line extends in the 1 st direction such that a length of the metal line in the 1 st direction is greater than a length in the 2 nd direction.
2 . The interconnect structure of claim 1 , wherein the sections of the metal line comprise 1 st , 2 nd and 3 rd sections along the 1 st direction, the 2 nd section being between the 1 st and 3 rd sections, and
wherein the 1 st section has a greater thickness than the 2 nd section, which has a greater thickness than the 3 rd section, in the 3 rd direction.
3 . The interconnect structure of claim 1 , wherein the vias have different protrusion heights in the 3 rd direction, and have different widths in the 1 st direction, and
wherein the protrusion heights of the vias are respectively measured from lowermost portions of the vias to uppermost portions of the vias.
4 . The interconnect structure of claim 3 , wherein the sections comprise 1 st and 2 nd sections, and the vias comprise 1 st and 2 nd vias protruded from the 1 st and 2 nd sections, respectively, and
wherein widths of the 1 st and 2 nd vias are smaller than lengths of the 1 st and 2 nd sections, respectively, in the 1 st direction.
5 . The interconnect structure of claim 4 , wherein each of the 1 st and 2 nd sections and each of the 1 st and 2 nd vias protruding therefrom is a single continuous structure without a connection surface therebetween.
6 . The interconnect structure of claim 5 , further comprising a dielectric structure isolating the 1 st and 2 nd vias from each other,
wherein each of the 1 st and 2 nd vias and the dielectric structure does not have a barrier metal layer therebetween.
7 . The interconnect structure of claim 1 , wherein each of the sections and each of the vias protruding therefrom is a single continuous structure without a connection surface therebetween.
8 . The interconnect structure of claim 7 , further comprising a dielectric structure isolating the vias from each other,
wherein each of the vias and the dielectric structure do not have a barrier metal layer therebetween.
9 . An integrated circuit comprising:
a plurality of circuit blocks comprising a plurality of semiconductor devices, respectively,
wherein the sections of the metal line of claim 1 are connected to the circuit blocks through the vias, respectively.
10 . An interconnect structure for an integrated circuit, the interconnect structure comprising:
a metal line comprising a plurality of sections extending in a 1 st direction perpendicular to a 2 nd direction; and
a plurality of vias respectively protruding from the plurality of sections, the vias having different protrusion heights in a 3 rd direction perpendicular to the 1 st direction and the 2 nd direction, and different widths in at least one of the 1 st direction and the 2 nd direction, wherein the protrusion heights of the vias are respectively measured from lowermost portions of the vias to uppermost portions of the vias,
wherein the metal line extends in the 1 st direction such that a length of the metal line in the 1 st direction is greater than a length in the 2 nd direction,
wherein the vias comprise 1 st and 2 nd vias respectively protruding from 1 st and 2 nd sections among the plurality of sections of the metal line, and
wherein a lowermost portion of the 1 st via is non-coplanar with a lowermost portion of the 2 nd via, and an uppermost portion of the 1 st via is coplanar with an uppermost portion of the 2 nd via.
11 . The interconnect structure of claim 10 ,
wherein the 1 st via has a smaller protrusion height than the 2 nd via, and
wherein the 1 st via has a greater width than the 2 nd via in the 1 st direction.
12 . The interconnect structure of claim 10 , wherein the sections of the metal line have different thicknesses in the 3 rd direction.
13 . The interconnect structure of claim 12 ,
wherein widths of the 1 st and 2 nd vias are smaller than lengths of the 1 st and 2 nd sections, respectively, in at least one of the 1 st and 2 nd directions.
14 . The interconnect structure of claim 13 , wherein each of the 1 st and 2 nd sections and each of the 1 st and 2 nd vias protruding therefrom is a single continuous structure without a connection surface therebetween.
15 . The interconnect structure of claim 14 , further comprising a dielectric structure isolating the vias from each other,
wherein each of the 1 st and 2 nd vias and the dielectric structure do not have a barrier metal layer therebetween.
16 . The interconnect structure of claim 10 , wherein each of the sections and each of the vias protruding therefrom is a single continuous structure without a connection surface therebetween.
17 . The interconnect structure of claim 16 , further comprising a dielectric structure isolating the vias from each other,
wherein each of the vias and the dielectric structure do not have a barrier metal layer therebetween.
18 . An integrated circuit comprising:
a plurality of circuit blocks comprising a plurality of semiconductor devices, respectively,
wherein the sections of the metal line of claim 10 are connected to the circuit blocks through the vias, respectively.
19 . The integrated circuit of claim 9 , wherein the semiconductor devices have respectively different performance characteristics comprising power consumption.
20 . The integrated circuit of claim 18 , wherein the semiconductor devices have respectively different performance characteristics comprising power consumption.