IP Library Patent Application 17849352
Patent Application
App. No. 17/849,352

COPPER RINGS FOR BGA COUNT REDUCTION IN SMALL FORM FACTOR PACKAGES

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Quick Facts
Patent No.
US None
App. No.
17/849,352
Abstract

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a die. In an embodiment, a package substrate is coupled to the die. In an embodiment, a ring is provided under the package substrate. In an embodiment, the ring comprises a conductive material. In an embodiment, the electronic package further comprises balls outside of the ring.

Claims (44)

1 . An electronic package, comprising:

a die;

a package substrate coupled to the die;

a ring under the package substrate, wherein the ring comprises a conductive material; and

balls outside of the ring.

2 . The electronic package of claim 1 , further comprising:

a second ring around the first ring.

3 . The electronic package of claim 2 , wherein the second ring comprises a plurality of segments.

4 . The electronic package of claim 3 , wherein the plurality of segments are configured to be coupled to different power rails.

5 . The electronic package of claim 3 , wherein the plurality of segments includes five or more segments.

6 . The electronic package of claim 1 , wherein the ring is configured to be grounded.

7 . The electronic package of claim 1 , further comprising:

a plurality of dies coupled to the package substrate.

8 . The electronic package of claim 1 , further comprising a capacitor within the ring.

9 . The electronic package of claim 8 , wherein a standoff height of the capacitor is greater than a standoff height of the ring.

10 . The electronic package of claim 8 , wherein a standoff height of the capacitor is less than a standoff height of the ring.

11 . The electronic package of claim 1 , wherein a first row of balls outside of the ring are functional balls.

12 . The electronic package of claim 1 , wherein the ring is at least partially within a footprint of the die.

13 . A package substrate, comprising:

a substrate with a first surface and a second surface opposite from the first surface;

an array of balls on the second surface of the substrate, wherein the array of balls includes a cavity;

a first ring inside the cavity;

a second ring inside the cavity and around the first ring; and

capacitors in the cavity.

14 . The package substrate of claim 13 , wherein the cavity is a rectangular cavity.

15 . The package substrate of claim 13 , wherein the first ring is electrically isolated from the second ring.

16 . The package substrate of claim 13 , wherein the second ring includes a plurality of segments, and wherein each segment is electrically isolated from each other.

17 . The package substrate of claim 16 , wherein the plurality of segments are configured to be held at different voltages during operation of the package substrate.

18 . The package substrate of claim 13 , wherein the first ring is configured to be held at a ground voltage during operation of the package substrate.

19 . The package substrate of claim 13 , wherein a first row of bumps around a perimeter of the cavity are functional bumps.

20 . The package substrate of claim 13 , wherein a standoff height of the capacitor is different than a standoff height of the first ring or the second ring.

21 . The package substrate of claim 13 , further comprising:

a die coupled to the first surface of the package substrate.

22 . The package substrate of claim 21 , wherein the first ring is at least partially within a footprint of the die.

23 . An electronic system, comprising:

a board;

a package substrate coupled to the board, wherein the package substrate comprises:

a first ring between the package substrate and the board;

a second ring between the package substrate and the board, wherein the second ring is around the first ring: and

balls between the package substrate and the board, wherein the balls are outside of the second ring; and

a die coupled to the package substrate.

24 . The electronic system of claim 23 , further comprising:

a plurality of capacitors within a perimeter of the first ring.

25 . The electronic system of claim 23 , wherein the first ring is configured to be grounded, and wherein the second ring comprises a plurality of segments that are configured to be held at different voltages.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076008/0329 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2023
From: NAGARAJAN, KAVITHA; LIM, MIN SUET; GOH, ENG HUAT; KAMGAING, TELESPHOR; YOON, CHEE KHEONG; WONG, JOOI WAH; LIM, CHU AUN
To: INTEL CORPORATION
Reel/Frame 063700/0545 →