Systems and methods for performing instructions to convert to 16-bit floating-point format
Disclosed embodiments relate to systems and methods for performing instructions to convert to 16-bit floating-point format. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a first source vector comprising N single-precision elements, and a destination vector comprising at least N 16-bit floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the specified source vector to 16-bit floating-point, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.
1. A processor comprising:
fetch circuitry to fetch a vector conversion instruction having fields to specify an opcode and locations of a first source vector comprising a first plurality of single-precision elements that are each a 32-bit floating point format of a sign bit, an 8-bit exponent, and a 24-bit significand, a second source vector comprising a second plurality of single-precision elements that are each the 32-bit floating point format of the sign bit, the 8-bit exponent, and the 24-bit significand, and a single destination vector comprising a number of 16-bit floating-point elements that is at least a number of the first plurality and the second plurality, the opcode to indicate execution circuitry is to convert each of the 32-bit floating point format elements of the first source vector and the second source vector to a half-precision 16-bit floating-point format of a sign bit, a 5-bit exponent, and an 11-bit significand, and to store each converted element into a corresponding location of the single destination vector as a resultant of the vector conversion instruction;
decode circuitry to decode the fetched instruction; and
the execution circuitry to respond to the decoded instruction as specified by the opcode.
2. The processor of claim 1 , wherein the conversion includes truncation and rounding.
3. The processor of claim 2 , wherein the execution circuitry performs the rounding according to a nearest even rounding rule.
4. The processor of claim 1 , wherein the locations of each of the first source vector, the second source vector, and the single destination vector are corresponding vector registers.
5. The processor of claim 1 , wherein the locations of each of the first source vector and the single destination vector are corresponding vector registers and the second source vector is a memory location.
6. The processor of claim 1 , wherein the number of the 16-bit floating-point elements in the single destination vector is specified by the vector conversion instruction.
7. The processor of claim 6 , wherein the number is selectable between 8, 16, and 32.
8. The processor of claim 1 , wherein the execution circuitry is configured to generate the number of the 16-bit floating-point elements of the single destination vector in parallel.
9. A method executed by a processor, the method comprising:
fetching, using fetch circuitry, a vector conversion instruction having fields to specify an opcode and locations of a first source vector comprising a first plurality of single-precision elements that are each a 32-bit floating point format of a sign bit, an 8-bit exponent, and a 24-bit significand, a second source vector comprising a second plurality of single-precision elements that are each the 32-bit floating point format of the sign bit, the 8-bit exponent, and the 24-bit significand, and a single destination vector comprising a number of 16-bit floating-point elements that is at least a number of the first plurality and the second plurality, the opcode to indicate execution circuitry is to convert each of the 32-bit floating point format elements of the first source vector and the second source vector to a half-precision 16-bit floating-point format of a sign bit, a 5-bit exponent, and an 11-bit significand, and to store each converted element into a corresponding location of the single destination vector as a resultant of the vector conversion instruction;
decoding, using decode circuitry, the fetched instruction; and
responding, using execution circuitry, to the decoded instruction as specified by the opcode.
10. The method of claim 9 , wherein the conversion includes truncation and rounding.
11. The method of claim 10 , wherein the execution circuitry performs the rounding according to a nearest even rounding rule.
12. The method of claim 9 , wherein the locations of each of the first source vector, the second source vector, and the single destination vector are corresponding vector registers.
13. The method of claim 9 , wherein the locations of each of the first source vector and the single destination vector are corresponding vector registers and the second source vector is a memory location.
14. The method of claim 9 , wherein the number of the 16-bit floating-point elements in the single destination vector is specified by the vector conversion instruction.
15. The method of claim 14 , wherein the number is selectable between 8, 16, and 32.
16. The method of claim 9 , wherein the execution circuitry generates the number of the 16-bit floating-point elements of the single destination vector in parallel.
17. A non-transitory machine-readable medium containing code that, when executed by a processor, cause the processor to respond by:
fetching, using fetch circuitry, a vector conversion instruction having fields to specify an opcode and locations of a first source vector comprising a first plurality of single-precision elements that are each a 32-bit floating point format of a sign bit, an 8-bit exponent, and a 24-bit significand, a second source vector comprising a second plurality of single-precision elements that are each the 32-bit floating point format of the sign bit, the 8-bit exponent, and the 24-bit significand, and a single destination vector comprising a number of 16-bit floating-point elements that is at least a number of the first plurality and the second plurality, the opcode to indicate execution circuitry is to convert each of the 32-bit floating point format elements of the first source vector and the second source vector to a half-precision 16-bit floating-point format of a sign bit, a 5-bit exponent, and an 11-bit significand, and to store each converted element into a corresponding location of the single destination vector as a resultant of the vector conversion instruction;
decoding, using decode circuitry, the fetched instruction; and
responding, using execution circuitry, to the decoded instruction as specified by the opcode.
18. The non-transitory machine-readable medium of claim 17 , wherein the conversion includes truncation and rounding.
19. The non-transitory machine-readable medium of claim 18 , wherein when the execution circuitry performs the rounding according to a nearest even rounding rule.
20. The non-transitory machine-readable medium of claim 17 , wherein the locations of each of the first source vector, the second source vector, and the single destination vector are corresponding vector registers.
21. The non-transitory machine-readable medium of claim 17 , wherein the locations of each of the first source vector and the single destination vector are corresponding vector registers and the second source vector is a memory location.
22. The non-transitory machine-readable medium of claim 17 , wherein the number of the 16-bit floating-point elements in the single destination vector is specified by the vector conversion instruction.
23. The non-transitory machine-readable medium of claim 22 , wherein the number is selectable between 8, 16, and 32.
24. The non-transitory machine-readable medium of claim 17 , wherein the execution circuitry is configured to generate the number of the 16-bit floating-point elements of the single destination vector in parallel.