Analog non-volatile memory device using poly ferroelectric film with random polarization directions
View Patent ↗A semiconductor device includes a ferroelectric field-effect transistor (FeFET), wherein the FeFET includes a substrate; a source region in the substrate; a drain region in the substrate; and a gate structure over the substrate and between the source region and the drain region. The gate structure includes a gate dielectric layer over the substrate; a ferroelectric film over the gate dielectric layer; and a gate electrode over the ferroelectric film.
1. A semiconductor device comprising:
a substrate; and
a ferroelectric tunnel junction (FTJ) over the substrate, the FTJ comprising:
a bottom electrode in or over the substrate;
a ferroelectric layer over the bottom electrode; and
a top electrode over the ferroelectric layer, wherein a tunneling electroresistance (TER) of the FTJ is adjustable and have more than two different values that changes linearly from a first TER value to a second TER value.
2. The semiconductor device of claim 1 , wherein in a top view, the top electrode and the ferroelectric layer have a same first surface area.
3. The semiconductor device of claim 2 , further comprising:
a dielectric layer between the bottom electrode and the ferroelectric layer; and
an internal metal layer between dielectric layer and the ferroelectric layer.
4. The semiconductor device of claim 3 , wherein in the top view, the internal metal layer and the dielectric layer have a same second surface area that is larger than the first surface area.
5. The semiconductor device of claim 3 , wherein the bottom electrode is a doped region of the substrate.
6. The semiconductor device of claim 3 , wherein the bottom electrode is a metal-containing material disposed on an upper surface of the substrate.
7. The semiconductor device of claim 6 , wherein the bottom electrode is a metal fin protruding above the upper surface of the substrate, wherein the dielectric layer extends long first sidewalls and a first upper surface of the metal fin.
8. The semiconductor device of claim 7 , wherein the internal metal layer extends along second sidewalls and a second upper surface of the dielectric layer.
9. The semiconductor device of claim 8 , wherein the ferroelectric layer is disposed on a third upper surface of the internal metal layer, wherein third sidewalls of the internal metal layer are free of the ferroelectric layer.
10. The semiconductor device of claim 1 , wherein the TER of the FTJ is adjustable and is configured to be adjusted by applying, between the top electrode and the bottom electrode, a sequence of voltage pulses with increasing or decreasing voltages.
11. The semiconductor device of claim 1 , wherein the ferroelectric layer comprises a doped hafnium oxide.
12. A semiconductor device comprising:
a substrate; and
a ferroelectric tunnel junction (FTJ) over the substrate, the FTJ comprising:
a bottom electrode over the substrate;
a dielectric layer over the bottom electrode;
an internal metal layer over the dielectric layer, wherein in a top view, the internal metal layer overlaps with the dielectric layer and has a same first surface area as the dielectric layer;
a ferroelectric layer over the internal metal layer; and
a top electrode over the ferroelectric layer, wherein in the top view, the top electrode overlaps with the ferroelectric layer and has a same second surface area as the ferroelectric layer, wherein the second surface area is smaller than the first surface area.
13. The semiconductor device of claim 12 , wherein a tunneling electroresistance (TER) of the FTJ is adjustable and have more than two different values.
14. The semiconductor device of claim 12 , wherein a tunneling electroresistance (TER) of the FTJ is adjustable and is configured to be adjusted by applying, between the top electrode and the bottom electrode, a sequence of voltage pulses with increasing or decreasing voltages.
15. The semiconductor device of claim 12 , wherein the ferroelectric layer is a doped hafnium oxide.
16. The semiconductor device of claim 15 , wherein the ferroelectric layer comprises a plurality of grains with random polarization directions.
17. A semiconductor device comprising:
a ferroelectric field-effect transistor (FeFET) comprising:
a substrate;
a source region in the substrate;
a drain region in the substrate; and
a gate structure over the substrate and between the source region and the drain region, wherein the gate structure comprises:
a gate dielectric layer over the substrate;
a ferroelectric film over the gate dielectric layer; and
a gate electrode over the ferroelectric film, wherein a threshold voltage of the FeFET is programmable and is configured to be programmed by a sequence of voltage pulses having continuously increasing or continuously decreasing amplitudes.
18. The semiconductor device of claim 17 , wherein the threshold voltage of the FeFET has more than two values that change linearly within a pre-determined range.
19. The semiconductor device of claim 17 , wherein the gate structure further comprises an internal metal layer between the gate dielectric layer and the ferroelectric film.
20. The semiconductor device of claim 17 , wherein the ferroelectric film comprises doped hafnium oxide, wherein the doped hafnium oxide is a hafnium oxide doped by silicon, aluminum, zirconium, gadolinium, or yttrium.