Analog non-volatile memory device using poly ferrorelectric film with random polarization directions
View Patent ↗A semiconductor device includes a ferroelectric field-effect transistor (FeFET), wherein the FeFET includes a substrate; a source region in the substrate; a drain region in the substrate; and a gate structure over the substrate and between the source region and the drain region. The gate structure includes a gate dielectric layer over the substrate; a ferroelectric film over the gate dielectric layer; and a gate electrode over the ferroelectric film.
1. A semiconductor device comprising:
a substrate; and
a ferroelectric tunnel junction (FTJ) over the substrate, the FTJ comprising:
a first capacitor comprising:
a bottom electrode over the substrate;
a dielectric layer over the bottom electrode; and
an internal metal layer over the dielectric layer; and
a second capacitor coupled in series with the first capacitor, comprising:
the internal metal layer;
a ferroelectric layer over the internal metal layer; and
a top electrode over the ferroelectric layer, wherein a first capacitance of the first capacitor is larger than the second capacitance of the second capacitor.
2. The semiconductor device of claim 1 , wherein in a top view, the internal metal layer has a same first surface area as the dielectric layer, and the top electrode has a same second surface area as the ferroelectric layer, wherein the second surface area is smaller than the first surface area.
3. The semiconductor device of claim 2 , wherein in the top view, the internal metal layer and the dielectric layer have a same first boundary, and the top electrode and the ferroelectric layer have a same second boundary.
4. The semiconductor device of claim 1 , wherein a tunneling electroresistance (TER) of the FTJ is adjustable and has more than two different values.
5. The semiconductor device of claim 1 , wherein a tunneling electroresistance (TER) of the FTJ is adjustable by applying, between the top electrode and the bottom electrode, a sequence of voltage pulses with increasing or decreasing voltages.
6. The semiconductor device of claim 5 , wherein the TER has more than two different values.
7. The semiconductor device of claim 1 , wherein the bottom electrode is a doped region of the substrate.
8. The semiconductor device of claim 1 , wherein the bottom electrode is a metal-containing material disposed on an upper surface of the substrate.
9. The semiconductor device of claim 1 , wherein the ferroelectric layer is a hafnium oxide doped by a dopant.
10. The semiconductor device of claim 1 , wherein the ferroelectric layer comprises a plurality of grains with random polarization directions.
11. A semiconductor device comprising:
a substrate; and
a ferroelectric tunnel junction (FTJ) over the substrate, the FTJ comprising:
a fin structure protruding above the substrate;
a dielectric layer extending along sidewalls of the fin structure and along an upper surface of the fin structure;
an internal metal layer over the dielectric layer;
a ferroelectric layer over an upper surface of the internal metal layer distal from the substrate, wherein sidewalls of the internal metal layer along the sidewalls of the fin structure are free of the ferroelectric layer; and
a top electrode over the ferroelectric layer.
12. The semiconductor device of claim 11 , wherein the fin structure is a metal fin protruding above the substrate.
13. The semiconductor device of claim 11 , wherein the fin structure and the substrate comprise a same semiconductor material doped by a dopant.
14. The semiconductor device of claim 13 , further comprising another dielectric layer on an upper surface of the substrate facing the fin structure, wherein a lower portion of the fin structure is embedded in the another dielectric layer, and an upper portion of the fin structure protrudes above the another dielectric layer.
15. The semiconductor device of claim 14 , wherein the dielectric layer extends along the upper portion of the fin structure but not along the lower portion of the fin structure.
16. The semiconductor device of claim 11 , wherein a tunneling electroresistance (TER) of the FTJ is adjustable and is configured to be adjusted by applying, between the top electrode and the fin structure, a sequence of voltage pulses with increasing or decreasing voltages.
17. A memory device comprising:
a switching transistor, wherein a gate terminal of the switching transistor is coupled to a word line (WL) of the memory device, and a drain terminal of the switching transistor is coupled to a programming line (PRL) of the memory device; and
a ferroelectric field-effect transistor (FeFET) coupled to the switching transistor, the FeFET comprising:
a source region;
a drain region; and
a gate structure between the source region and the drain region, wherein the gate structure comprises:
a gate dielectric layer;
a ferroelectric film over the gate dielectric layer; and
a gate electrode over the ferroelectric film, wherein a threshold voltage of the FeFET is programmable and has more than two values that change continuously within a pre-determined range, wherein the gate electrode of the FeFET is coupled to a source terminal of the switching transistor, the drain region of the FeFET is coupled to a bit line (BL) of the memory device, and the source region of the FeFET is coupled to an output line (SL) of the memory device.
18. The memory device of claim 17 , wherein the gate structure of the FeFET further comprises an internal metal layer between the gate dielectric layer and the ferroelectric film.
19. The memory device of claim 17 , wherein the threshold voltage of the FeFET is configured to be programmed by a sequence of voltage pulses having continuously increasing or continuously decreasing amplitudes.
20. The memory device of claim 17 , wherein the ferroelectric film comprises hafnium oxide doped by a dopant, wherein the dopant is silicon, aluminum, zirconium, gadolinium, or yttrium.