Semiconductor device and manufacturing method thereof
A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.
1. A semiconductor device, comprising:
a channel region disposed over a substrate and extending in a first direction; and
a gate structure disposed over the channel region, wherein:
the gate structure includes:
a gate dielectric layer disposed over the channel region and entirely made of a high-k dielectric material;
a work function adjustment material (WFM) layer disposed over the gate dielectric layer;
a ferroelectric material layer disposed over the WFM layer; and
an upper conductive layer disposed over the ferroelectric material layer, and
the ferroelectric material layer has a U-shape cross section along the first direction,
the U-shape has a horizontal portion and vertical portions vertically extending from ends of the horizontal portion in a direction away from the substrate,
the ferroelectric material layer fully covers and is in direct contact with an uppermost portion, which is a farthest portion from the substrate in the direction away from the substrate, of the gate dielectric layer and the WFM layer, and
the WFM layer fully fills a space defined by the gate dielectric layer and the horizontal portion of the ferroelectric material layer.
2. The semiconductor device of claim 1 , wherein the WFM layer does not have a U-shape cross section along the first direction.
3. The semiconductor device of claim 2 , wherein the WFM layer includes one or more layers of Ti, TiN, TaN, TiC, Co, HfTi, TiSi or TaSi.
4. The semiconductor device of claim 2 , wherein the WFM layer includes one or more layers of TiAl, TiAlC, TaAlC, or Al.
5. The semiconductor device of claim 1 , wherein:
the upper conductive layer includes:
a first conductive layer disposed on the ferroelectric material layer; and
a second conductive layer disposed over the first conductive layer, and the first conductive layer has a U-shape cross section along the first direction.
6. The semiconductor device of claim 5 , wherein the second conductive layer does not have a U-shape cross section along the first direction.
7. The semiconductor device of claim 5 , wherein:
the first conductive layer includes one or more layers of Ti, TiN, Ta and TaN, and
the second conductive layer includes one or more layers of W, Co, Ni and Cu.
8. The semiconductor device of claim 1 , wherein the ferroelectric material layer includes one or more layers of ZrAlSiO, HfO 2 , HfZrO 2 , hafnium silicate, HfAlO, or HfO 2 doped with Si (HfSiO x ).
9. The semiconductor device of claim 1 , wherein:
the gate structure further includes a gate cap insulating layer disposed over the upper conductive layer, and
a bottom of the gate cap insulating layer is substantially flat.
10. The semiconductor device of claim 1 , wherein a thickness of the WFM layer is in a range from 5 nm to 50 nm.
11. A semiconductor device, comprising:
a channel region, which is a part of a fin structure, disposed over a substrate and extending in a first direction; and
a gate structure disposed over the channel region, wherein:
the gate structure includes:
a gate dielectric layer disposed over the channel region and entirely made of a high-k dielectric material;
a lower conductive gate layer disposed over the gate dielectric layer;
a ferroelectric material layer disposed over the lower conductive gate layer;
an upper conductive gate layer disposed over the ferroelectric material layer; and
sidewall spacers in direct contact with the gate dielectric layer and the ferroelectric material layer,
the ferroelectric material layer fully covers and is in direct contact with an uppermost portion of the gate dielectric layer, which is a farthest part of the gate dielectric layer in a direction away from the substrate, and the lower conductive gate layer, and has a U-shape cross section along the first direction, the U-shape having a horizontal portion and vertical portions vertically extending from ends of the horizontal portion in the direction away from the substrate,
the uppermost portion of the gate dielectric layer is located below a bottommost portion, which is a closest portion to the substrate, of the upper conductive gate layer, and
the lower conductive gate layer does not have a U-shape and an entire upper surface of the lower conductive gate layer is in contact with the ferroelectric material layer.
12. The semiconductor device of claim 11 , wherein the ferroelectric material layer is one selected from the group consisting of HfZrO 2 and HfSiO x .
13. The semiconductor device of claim 11 , wherein a thickness of the lower conductive gate layer is in a range from 5 nm to 50 nm.
14. The semiconductor device of claim 11 , wherein a thickness of the ferroelectric material layer above the lower conductive gate layer is in a range from 2 nm to 20 nm.
15. A semiconductor device, comprising:
a first field effect transistor (FET) including a first gate structure, wherein:
the first gate structure of the first FET includes:
a first gate dielectric layer made of a dielectric material;
a first conductive layer made of a first conductive material;
a ferroelectric material layer disposed over the first gate dielectric layer and the first conductive layer;
a second conductive layer disposed over the ferroelectric material layer; and
a first gate cap insulating layer disposed in direct contact with the ferroelectric material layer and the second conductive layer,
the first gate structure extends in a first direction,
the ferroelectric material layer is in direct contact with the first gate dielectric layer and the first conductive layer, and has a U-shape in a cross section along a second direction crossing the first direction,
the U-shape has a horizontal portion and vertical portions vertically extending from ends of the horizontal portion in a direction away from the substrate, and
the first conductive layer fully fills a space defined by the first gate dielectric layer and the horizontal portion of the ferroelectric material layer.
16. The semiconductor device of claim 15 , wherein:
the first gate structure of the first FET further includes a third conductive layer disposed over the second conductive layer and the ferroelectric material layer,
the second conductive layer of the first gate structure has a U-shape in a cross section along the second direction, and
the U-shape has a horizontal portion and vertical portions vertically extending from ends of the horizontal portion in a direction away from the substrate.
17. The semiconductor device of claim 16 , wherein:
the third conductive layer does not have a U-shape and an entire upper surface of the third conductive layer is in contact with the first gate cap insulating layer.
18. The semiconductor device of claim 16 , further comprising a second FET including a second gate structure having a different structure than the first gate structure,
wherein the second gate structure of the second FET includes:
a second gate dielectric layer made of the dielectric material;
a fourth conductive layer made of the first conductive material;
a fifth conductive layer made of a second conductive material; and
a second gate cap insulating layer disposed in direct contact with the fourth conductive layer and the fifth conductive layer.
19. The semiconductor device of claim 18 , wherein the first gate structure includes no layer made of the second conductive material below the ferroelectric material layer.
20. The semiconductor device of claim 16 , wherein a bottom of the first gate cap insulating layer is substantially flat.