Pixel device on deep trench isolation (DTI) structure for image sensor

1. A CMOS image sensor, comprising:

a pixel region comprising a photodiode disposed within a substrate;

a deep trench isolation (DTI) ring enclosing the photodiode from top view and extending from a back-side to a first position within the substrate from cross-sectional view;

a pair of shallow trench isolation (STI) structures respectively disposed at an inner periphery and an outer periphery sandwiching the DTI ring from top view and extending from a front-side to a second position within the substrate from cross-sectional view;

a pixel device disposed at the front-side of the substrate directly overlying the DTI ring, the pixel device comprising a gate electrode disposed over the substrate and a pair of source/drain (S/D) regions disposed within the substrate and reaching on a top surface of the DTI ring.

2. The CMOS image sensor of claim 1 , wherein the DTI ring has a top surfaces locating at a position of the substrate vertically exceeding bottom surfaces of the pair of STI structures.

3. The CMOS image sensor of claim 2 , wherein the S/D regions of the pixel device have bottom surfaces locating at a position of the substrate higher than bottom surfaces of the pair of STI structures.

4. The CMOS image sensor of claim 2 , wherein the S/D regions of the pixel device have bottom surfaces laterally aligned with bottom surfaces of the pair of STI structures.

5. The CMOS image sensor of claim 2 , wherein the DTI ring has an outermost sidewall contacting a bottom surface of one of the pair of STI structures and an innermost sidewall contacting a bottom surface of the other one of the pair of STI structures.

6. The CMOS image sensor of claim 2 , wherein the pixel device is a source follower transistor, a reset transistor, or a row select transistor.

7. The CMOS image sensor of claim 1 , wherein the pixel device has outermost sidewalls of the S/D regions contacting an outermost sidewall of one of the pair of STI structures and innermost sidewalls of the S/D regions contacting innermost sidewall of the other one of the pair of STI structures.

8. The CMOS image sensor of claim 1 , wherein the DTI ring comprises silicon oxide.

9. The CMOS image sensor of claim 1 , further comprising:

an anti-reflection layer disposed on the back-side of the substrate;

wherein the anti-reflection layer has a non-flat bottom surface.

10. The CMOS image sensor of claim 9 , further comprising:

a conductive column disposed at a center region of the DTI ring and electrically connecting the S/D regions of the pixel device to a contact at the back-side of the substrate through the anti-reflection layer.

11. The CMOS image sensor of claim 1 , wherein the S/D regions of the pixel device comprise a silicide layer locating at an upper region of the S/D regions.

12. The CMOS image sensor of claim 1 , further comprising:

a floating diffusion well disposed within the substrate between the photodiode and the DTI ring; and

a transfer gate electrode arranged on the front-side of the substrate at a position laterally between the photodiode and the floating diffusion well and separated from the substrate by a gate dielectric.

13. The CMOS image sensor of claim 12 , wherein the transfer gate electrode and the gate dielectric extend to a position within the substrate.

14. A CMOS image sensor, comprising:

a substrate having a front-side and a back-side opposite to the front-side;

a pixel region disposed within the substrate and comprising a photodiode configured to convert radiation that enters the substrate from the back-side into an electrical signal;

a first shallow trench isolation (STI) structure and a second STI structure separated from one another, extending from the front-side of the substrate from a cross-sectional view, and respectively enclosing the photodiode from a top view;

a deep trench isolation (DTI) ring disposed between the first STI structure and the second STI structure and extending from the back-side of the substrate to meet the first STI structure and the second STI structure within the substrate; and

a pixel device disposed at the front-side of the substrate between the first and second STI structures, the pixel device comprising a pair of source/drain (S/D) regions directly contacting a top surface of the DTI ring.

15. The CMOS image sensor of claim 14 , wherein the pair of S/D regions directly contacts sidewalls of the first and second STI structures.

16. The CMOS image sensor of claim 14 , wherein the pixel device further comprises a gate electrode disposed over the substrate and crossing edges of the first STI structure and the second STI structure.

17. The CMOS image sensor of claim 14 , wherein a bisecting line of the first STI structure and the second STI structures laterally bisects the DTI ring.

18. The CMOS image sensor of claim 14 , wherein the pixel device is a source follower transistor, a reset transistor, or a row select transistor.

19. A CMOS image sensor, comprising:

a first shallow trench isolation (STI) structure and a second STI structure disposed at a peripheral of a pixel region from a front-side of a substrate;

a photodiode disposed in the pixel region from the front-side;

a transfer gate structure disposed aside of the photodiode and a floating diffusion well disposed at one side of the transfer gate structure opposite to the photodiode;

a pixel device comprising S/D regions disposed between the first STI structure and the second STI structure; and

a deep trench isolation (DTI) ring disposed from a back-side of the substrate extending into the substrate and between the first STI structure and the second STI structure from a cross-sectional view and enclosing the photodiode and the floating diffusion well from a top view;

wherein the DTI ring directly contacts the S/D regions of the pixel device.

20. The CMOS image sensor of claim 19 , wherein the S/D regions of the pixel device directly contact sidewalls of the first and second STI structures.