Semiconductor device with user defined operations and associated methods and systems
Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.
1. An apparatus comprising:
a memory array corresponding to a plurality of memory addresses, each memory address of the plurality of memory addresses associated with a first portion of the memory array configured to store user data and with a second portion of the memory array configured to store error-correcting code (ECC) data associated with the user data of the first portion when an ECC function of the apparatus is enabled;
a register configured to store one or more bits indicating an option from a plurality of options for interacting with the second portion of the memory array when the ECC function of the apparatus is disabled; and
circuitry configured to:
determine the indicated option based on the one or more bits stored in the register, and
interact with the second portion of the memory array based on the indicated option.
2. The apparatus of claim 1 , wherein the indicated option corresponds to storing additional user data, metadata, or both in the second portion when the ECC function is disabled, the metadata including an operating temperature of the apparatus, a latency setting for accessing the memory array, a parameter for transmitting data, or a combination thereof.
3. The apparatus of claim 1 , wherein the register is further configured to indicate that the ECC function is disabled.
4. The apparatus of claim 1 , wherein the indicated option corresponds to retrieving the user data uncorrected by the ECC function or storing the user data without performing the ECC function.
5. The apparatus of claim 1 , wherein the indicated option corresponds to accessing the second portion of the memory array based on decoding a memory address of an access command directed to the memory array.
6. The apparatus of claim 1 , wherein the indicated option corresponds to enabling one or more address pins identifying the second portion of the memory array, the one or more address pins separate from a quantity of address pins corresponding to the plurality of memory addresses.
7. The apparatus of claim 1 , wherein the indicated option corresponds to enabling one or more data pins configured to transmit or receive data for the second portion of the memory array, the one or more data pins separate from a quantity of data pins configured to transmit or receive data for the first portion of the memory array.
8. The apparatus of claim 1 , wherein the indicated option corresponds to determining a burst length of the memory device, the burst length corresponding to the user data for the first portion and additional user data and/or metadata for the second portion.
9. A method comprising:
storing, in a register of a memory device, one or more bits corresponding to an option selected from a plurality of options for interacting with a memory array of the memory device when an error-correcting code (ECC) function of the memory device is disabled, the memory array corresponding to a plurality of memory addresses each associated with a first portion of the memory array configured to store user data and with a second portion of the memory array configured to store ECC data associated with the user data of the first portion when the ECC function of the memory device is enabled;
receiving, at the memory device, an access command associated with a memory address of the plurality of memory addresses; and
interacting with the second portion of the memory array in response to the access command and based at least in part on the indicated option.
10. The method of claim 9 , further comprising disabling the ECC function.
11. The method of claim 9 , further comprising decoding a first segment of a memory address associated with the access command to identify the second portion of the memory array.
12. The method of claim 9 , wherein interacting with the second portion of the memory array comprises retrieving the user data uncorrected by the ECC function or storing the user data without performing the ECC function.
13. The method of claim 9 , wherein interacting with the second portion of the memory array comprises enabling one or more address pins identifying the second portion of the memory array, the one or more address pins separate from a quantity of address pins corresponding to the plurality of memory addresses.
14. The method of claim 9 , wherein interacting with the second portion of the memory array comprises enabling one or more data pins configured to transmit or receive data for the second portion of the memory array, wherein the one or more data pins separate from a quantity of data pins configured to transmit or receive data for the first portion of the memory array.
15. A memory system comprising:
a host device; and
a memory device including:
a memory array corresponding to a plurality of memory addresses, each memory address of the plurality of memory addresses associated with a first portion of the memory array configured to store user data and with a second portion of the memory array configured to store error-correcting code (ECC) data associated with the user data of the first portion when an ECC function of the apparatus is enabled; and
a register configured to store one or more bits indicating an option from a plurality of options for interacting with the second portion of the memory array when the ECC function of the apparatus is disabled;
wherein the memory device is configured to:
determine the indicated option based on the one or more bits stored in the register, and
communicate with the host device based on the indicated option.
16. The memory system of claim 15 , wherein the host device is configured to disable the ECC function of the memory device.
17. The memory system of claim 15 , wherein the host device is configured to access the second portion of the memory array when the ECC function of the memory device is enabled.
18. The memory system of claim 15 , wherein the host device is configured to activate one or more channels coupled to one or more address pins identifying the second portion of the memory array, the one or more address pins separate from a quantity of address pins corresponding to the plurality of memory addresses.
19. The memory system of claim 15 , wherein the host device is configured to activate one or more channels coupled to one or more data pins configured to transmit or receive data for the second portion of the memory array, wherein the one or more data pins separate from a quantity of data pins configured to transmit or receive data for the first portion of the memory array.
20. The memory system of claim 15 , wherein the host device is configured to communicate with the memory device for a burst length corresponding to the user data for the first portion and additional user data and/or metadata for the second portion.