Semiconductor device with user defined operations and associated methods and systems
Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.
1. An apparatus comprising:
a memory array corresponding to a plurality of memory addresses, each memory address of the plurality of memory addresses associated with a first portion of the memory array configured to store user data and with a second portion of the memory array configured to store error-correcting code (ECC) data associated with the user data of the first portion when an ECC function of the apparatus is enabled;
a register configured to store one or more bits corresponding to a plurality of options for a host device to access the memory array when the ECC function is disabled; and
circuitry configured to:
select an option from the plurality of options based on an input from the host device when the ECC function is disabled;
update the one or more bits in the register based on the selected option; and
communicate with the host device in accordance with the selected option when the ECC function is disabled.
2. The apparatus of claim 1 , wherein the circuitry is further configured to bypass an ECC circuit that performs the ECC function for the user data.
3. The apparatus of claim 1 , wherein the selected option includes retrieving the user data uncorrected by the ECC function or storing the user data without performing the ECC function.
4. The apparatus of claim 1 , wherein the selected option includes decoding a first segment of a memory address associated with an access command to identify the second portion of the memory array.
5. The apparatus of claim 4 , wherein the first segment of the memory address corresponds to one or more address pins that are separate from a quantity of address pins corresponding to the plurality of memory addresses.
6. The apparatus of claim 1 , wherein the selected option includes accessing the second portion of the memory array based on a memory address of an access command, the memory address corresponding to a memory address of the plurality of memory addresses.
7. The apparatus of claim 1 , wherein the selected option includes enabling a first set of data pins corresponding to additional data for the second portion of the memory array.
8. The apparatus of claim 7 , wherein the first set of data pins are separate from a second set of data pins corresponding to the user data for the first portion of the memory array.
9. The apparatus of claim 1 , wherein the selected option includes determining a burst length for communicating with the host device, the burst length corresponding to the user data for the first portion and additional data for the second portion.
10. The apparatus of claim 9 , wherein communicating with the host device includes transmitting or receiving the user data and the additional data for the burst length.
11. A method comprising:
receiving, at a memory device, a signaling that indicates an option selected from a plurality of options for a host device to access a memory array of the memory device when an error-correcting code (ECC) function of the memory device is disabled, the memory array corresponding to a plurality of memory addresses each associated with a first portion of the memory array configured to store user data and with a second portion of the memory array configured to store ECC data associated with the user data of the first portion when an ECC function of the memory device is enabled;
storing, in a register of the memory device, one or more bits corresponding to the option selected from the plurality of options;
receiving, at the memory device, an access command associated with a memory address of the plurality of memory addresses;
accessing the first portion of the memory array, the second portion of the memory array, or both in response to the access command and based at least in part on the selected option as indicated by the one or more bits stored in the register; and
communicating with the host device in accordance with the selected option.
12. The method of claim 11 , further comprising decoding a first segment of the memory address associated with the access command to identify the second portion of the memory array.
13. The method of claim 11 , wherein accessing the first portion of the memory array comprises retrieving the user data uncorrected by the ECC function or storing the user data without performing the ECC function.
14. The method of claim 11 , further comprising enabling a first set of data pins corresponding to additional data for the second portion of the memory array.
15. The method of claim 11 , further comprising determining a burst length for communicating with the host device, the burst length corresponding to the user data for the first portion and additional data for the second portion.
16. A memory system comprising:
a host device; and
a memory device including:
a memory array corresponding to a plurality of memory addresses, each memory address of the plurality of memory addresses corresponding to a first portion of the memory array configured to store user data and to a second portion of the memory array configured to store error checking and correcting (ECC) data associated with the user data of the first portion when an ECC function of the memory device is enabled; and
a register configured to store one or more bits corresponding to a plurality of options for the host device to access the memory array when the ECC function is disabled;
wherein the host device is configured to transmit an input directed to the plurality of options to access the memory array, and
wherein the memory device is configured to:
select an option from the plurality of options based on the input from the host device;
update the one or more bits in the register based on the selected option; and
communicate with the host device in accordance with the selected option.
17. The memory system of claim 16 , wherein the host device is further configured to perform a separate ECC function that is different from the ECC function of the memory device.
18. The memory system of claim 16 , wherein the host device is further configured to generate a memory address comprising a first segment and a second segment, the first segment of the memory address corresponding to one or more address pins that are separate from a quantity of address pins corresponding to the second segment for the plurality of memory addresses.
19. The memory system of claim 16 , wherein the host device is further configured to activate one or more channels associated with a first set of data pins of the memory device, the first set of data pins corresponding to additional data for the second portion and separate from a second set of data pins corresponding to the user data for the first portion.
20. The memory system of claim 16 , wherein the host device is further configured to communicate with the memory device for a burst length corresponding to the user data for the first portion and additional data for the second portion.