Granted Patent B2

US 12,730,743 · App. 18/430,381 · Granted Sep 8, 2026

Inventor: Sujeet Ayyapureddi (Boise, ID)

Assignee: Micron Technology, Inc.

G06F12/0223G06F11/1044

Abstract

Claims (64)

1 . An apparatus comprising:

an address decoder configured to receive a column address comprising a plurality of bits;

a memory array comprising a plurality of column planes, wherein a portion of each of the plurality of column planes associated with a column select is configured to store metadata and a second portion of each of the plurality of column planes associated with a second column select is configured to store data; and

a mode register configured to store a first value or a second value, wherein:

when the first value is stored in the mode register, the memory array is configured to provide the metadata when a portion of the plurality of bits of the column address is a first state, wherein the portion of the plurality of bits of the column address comprises less than all of the column address, and

when the second value is stored in the mode register, the memory array is configured to provide the metadata when the portion of the plurality of bits is a second state.

2 . The apparatus of claim 1 , wherein the portion of the plurality of bits comprises one bit.

3 . The apparatus of claim 1 , wherein the portion of the plurality of bits of the column address comprises a tenth bit of the column address.

4 . The apparatus of claim 1 , wherein the mode register is configured to store a third value or a fourth value wherein the portion of the plurality of planes is configured to store the metadata when the third value is stored and the portion of the plurality of planes is configured to store data when the fourth value is stored.

5 . A system comprising:

a first plurality of memory devices each comprising one of a first plurality of mode registers and one of a first plurality of memory arrays comprising a first plurality of column planes, wherein a portion of each of the plurality of column planes associated with a column select is configured to store first metadata; and

a second plurality of memory devices each comprising one of a second plurality of mode registers and one of a second plurality of memory arrays comprising a second plurality of column planes, wherein a portion of each of the second plurality of column planes associated with the column select is configured to store second metadata;

wherein the first plurality of mode registers and the second plurality of mode registers are configured to store a first value or a second value, wherein:

when the first value is stored in the first plurality of mode registers, the first plurality of memory devices is configured to provide the first metadata when a portion of a plurality of bits of a column address is a first state,

when the first value is stored in the second plurality of mode registers, the second plurality of memory devices is configured to provide the second metadata when the portion of the plurality of bits of the column address is the first state,

when the second value is stored in the first plurality of mode registers, the first plurality of memory devices is configured to provide the first metadata when the portion of the plurality of bits of the column address is a second state,

when the second value is stored in the second plurality of mode registers, the second plurality of memory devices is configured to provide the second metadata when the portion of the plurality of bits of the column address is the second state,

wherein the portion of the plurality of bits of the column address comprises less than all of the column address.

6 . The system of claim 5 , wherein when the first plurality of mode registers stores the first value, the second plurality of mode registers stores the second value, and when the first plurality of mode registers stores the second value, the second plurality of mode registers stores the first value.

7 . The system of claim 5 , further comprising a controller, wherein the controller is configured to:

provide the first value or the second value to the first plurality of mode registers or the second plurality of mode registers;

provide the column address;

ignore the first metadata provided from the first plurality of memory devices or the second metadata provided from second plurality of memory devices when the portion of the plurality of bits is in the first state or the second state based, at least in part, on whether the first value or the second value is stored in the first plurality of mode registers or the second plurality of mode registers; and

provide a mode register write command to cause the first value or the second value to be stored in the first plurality of mode registers or the second plurality of registers.

8 . The system of claim 5 , wherein the first plurality of memory devices comprises four memory devices and the second plurality of memory devices comprises four memory devices.

9 . The system of claim 6 , wherein the first plurality and the second plurality of memory devices are configured to operate in a x4 mode.

10 . The system of claim 5 wherein the portion of the plurality of bits comprises a bit wherein the bit comprises a tenth bit of the column address.

11 . A method comprising:

receiving a mode register write command at a memory device;

responsive to the mode register write command, writing a first value or a second value to a mode register of the memory device;

receiving a column address at the memory device, wherein the column address comprises a plurality of bits;

responsive, at least in part, to the column address:

providing from the memory device, metadata stored in bit lines associated with a column select of each column plane of a plurality of column planes of a memory array of the memory device when a portion of the plurality of bits is a first state when the first value is stored in the mode register, wherein the portion of the plurality of bits of the column address comprises less than all of the column address; and

providing from the memory device, the metadata when the portion of the plurality of bits is a second state when the second value is stored in the mode register.

12 . The method of claim 11 , further comprising receiving a read command associated with the column address, wherein providing the metadata is further responsive to the read command.

13 . The method of claim 11 , further comprising storing the metadata in a portion of a plurality of column planes of a memory array of the memory device, wherein the metadata is associated with data stored in remaining portions of the plurality of column planes.

14 . The method of claim 11 , wherein the portion of the plurality of bits of the column address comprises a tenth bit of the column address.

15 . The method of claim 11 , further comprising:

receiving a second mode register write command at a second memory device;

responsive to the second mode register write command, writing the first value or the second value to a second mode register of the second memory device;

receiving the column address at the second memory device;

responsive, at least in part, to the column address:

providing from the second memory device, second metadata when the portion of the plurality of bits is the first state when the first value is stored in the second mode register; and

providing from the memory device, the second metadata when the portion of the plurality of bits is the second state when the second value is stored in the second mode register,

wherein the first value is written to the second mode register when the second value is written to the mode register and the second value is written to the second mode register when the first value is written to the mode register.

16 . A method comprising:

providing a mode register write command to a memory device from a controller;

providing a first value or a second value to be written to a mode register of the memory device;

providing a column address to the memory device, wherein the column address comprises a plurality of bits;

receiving metadata from the memory device when a portion of the plurality of bits is a first state when the first value is written to the mode register, wherein the portion of the plurality of bits of the column address comprises less than all of the column address, wherein the metadata is provided from a portion of each column plane of a plurality of column planes, wherein the portion is associated with a column select; and

receiving the metadata from the memory device when the portion of the plurality of bits is a second state when the second value is written to the mode register.

17 . The method of claim 16 , further comprising:

providing a read command to the memory device; and

receiving data from the memory device associated with the column address, wherein the data is associated with the metadata.

18 . The method of claim 16 , further comprising:

providing a second mode register write command to a second memory device from the controller;

providing the first value or the second value to be written to a second mode register of the second memory device from the controller;

providing the column address to the second memory device;

receiving second metadata from the memory device when the portion of the plurality of bits is the first state when the first value is written to the second mode register; and

receiving the second metadata from the memory device when the portion of the plurality of bits is the second state when the second value is written to the second mode register,

wherein the memory device is one of a first plurality of memory devices and the second memory device is one of a second plurality of memory devices, wherein all of the first plurality of memory devices received the first value and all of the second plurality of memory devices received the second value,

wherein the controller provides the first value to the second memory device when the controller provides the second value to the memory device and the controller provides the second value to the second memory device when the controller provides the first value to the memory device.

19 . The method of claim 16 , wherein the first value or the second value is provided to at least one command/address pin of the memory device.

20 . The method of claim 16 , wherein the portion of the plurality of bits comprises a bit, wherein the bit comprises a tenth bit of the column address.

Assignments (1)

Continuity (2)

References Cited (263)