Apparatuses and methods for enhanced metadata support
Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an x4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.
1 . A method comprising:
writing a value to a mode register of a memory device to set the memory device in a first mode or a second mode;
writing data and metadata to a memory array of the memory device;
addressing a first percentage of the memory array in the first mode or a second percentage of the memory array in the second mode; and
writing a first number of bits of metadata to the memory array in the first mode and writing a second number of bits of metadata to the memory array in the second mode, wherein the first number of bits and the second number of bits are different.
2 . The method of claim 1 , wherein the first mode and the second mode are both x4 modes of the memory device.
3 . The method of claim 1 , further comprising writing 64 bits of data and 4 bits of metadata to the memory array in the first mode and writing 64 bits of data and 8 bits of metadata to the memory array in the second mode.
4 . The method of claim 1 , further comprising:
generating a column address associated with one of a first range of column select values in the first mode or generated associated with one of a second range of column select values in the second mode, wherein the second range is larger than the first range; and
providing the column address as part of writing the data and the metadata to the memory array.
5 . The method of claim 1 , further comprising:
writing the data and the metadata to the memory array with a common latency in both the first and second modes.
6 . The method of claim 1 , further comprising reducing the first and second percentages each by a third percentage when single error correction double error detection (SECDED) error correcting code operation is supported.
7 . A method comprising:
writing a value to a mode register of a memory device to set a metadata mode of the memory device to one of a first mode or a second mode;
accessing a first percentage of addresses of the memory array of the memory device to store data when the metadata mode is in the first mode; and
accessing a second percentage of addresses of the memory array of the memory device to store data when the metadata mode is in the second mode, wherein the first percentage is greater than the second percentage.
8 . The method of claim 7 , wherein the first mode and the second mode are both x4 modes of the memory device.
9 . The method of claim 7 , further comprising writing 64 bits of data to the memory array in the first and the second modes.
10 . The method of claim 7 , further comprising setting aside an additional third percentage of addresses for storage of metadata when the metadata mode is in the second mode, wherein the third percentage is based on a difference between the first percentage and the second percentage.
11 . The method of claim 7 , wherein the first mode represents a four bit metadata mode and the second mode represents an eight bit metadata mode.
12 . The method of claim 7 , further comprising accessing the memory array one time to write the data in both the first mode and the second mode.
13 . The method of claim 7 , further comprising writing four bits of metadata to the memory array in the first mode and eight bits of metadata to the memory array in the second mode.
14 . A method comprising:
writing a value to a mode register of a memory device to set the memory device in a first mode or a second mode;
reading data and four bits of metadata from a memory array of the memory device while in the first mode; and
reading data and eight bits of metadata from a memory array of the memory device while in the second mode.
15 . The method of claim 14 , further comprising:
receiving data bits and metadata bits where an error is corrected in the data and metadata bits in the second mode; and
receiving data bits and metadata bits wherein an error is corrected in the data but not the metadata bits in the first mode.
16 . The method of claim 14 , further comprising:
addressing only an extra column plane of the memory array in the first mode to store the metadata; and
addressing the extra column plane and other data column planes of the memory array in the second mode to store metadata.
17 . The method of claim 14 , further comprising writing data and metadata to the memory array with a common latency in both the first and second modes.
18 . A system comprising:
a memory device comprising:
a mode register configured to store a value, wherein based on the value the memory device operates in a first mode or a second mode;
a memory bank comprising a first plurality of column planes, a second plurality of column planes, and an extra column plane; and
a column decoder configured to store data in a selected one of the first or the second plurality of column planes, parity bits in a non-selected one of the first or the second plurality of column planes, and metadata in the extra column plane as part of an access operation in the first mode and store data in the selected one of the first or the second plurality of column planes, parity bits in the non-selected one of the first or the second plurality of column planes, and metadata at least one of the non-selected one of the first or the second plurality of column planes or the extra column plane as part of an access operation in the second mode; and
a controller configured to write the value to the mode register to set the memory in the first mode or the second mode.
19 . The system of claim 18 , wherein the controller is configured to provide four metadata bits per access operation while in the first mode and eight bits of metadata per access operation in the second mode.
20 . The system of claim 18 , wherein the ECC circuit operates in a single error correction double error detection scheme in both the first mode and the second mode.
21 . The system of claim 18 , wherein the controller is configured to generate a column address as part of a write operation, wherein the column address is generated to be associated with a first range of column select values when the memory device is in the first mode and a second range of column select values when the memory device is in the second mode.