Memory controllers and memory systems including the same
A memory controller configured to control a memory module, the memory controller including processing circuitry configured to perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome, determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome, and output a decoding status flag indicating the type of error.
1. A memory controller configured to control a memory module, the memory controller comprising:
processing circuitry configured to,
perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome,
determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome, and
output a decoding status flag indicating the type of error.
2. The memory controller of claim 1 , wherein the processing circuitry is configured to:
output the decoding status flag indicating that a user data set of the read codeword includes a correctable error in response to the decision syndrome having a non-zero logic level;
generate a third syndrome indicating a position of the correctable error based on a second portion of the parity check matrix and the read codeword; and
correct the correctable error using the third syndrome to obtain a corrected user data set.
3. The memory controller of claim 1 , wherein the processing circuitry is configured to output the decoding status flag indicating that a user data set of the read codeword does not include errors in response to the decision syndrome having a zero logic level and the second syndrome having a zero logic level.
4. The memory controller of claim 1 , wherein the processing circuitry is configured to output the decoding status flag indicating that a user data set of the read codeword includes uncorrectable errors in response to the decision syndrome having a zero logic level and the second syndrome having a non-zero logic level.
5. The memory controller of claim 1 , wherein the read codeword includes a user data set, meta data associated with the user data set, error locator parity data, first error magnitude parity data and second error magnitude parity data.
6. The memory controller of claim 5 , wherein
the memory module includes a plurality of data chips, a first parity chip and a second parity chip;
the user data set is read from the plurality of data chips;
the meta data and the error locator parity data are read from the first parity chip; and
the first error magnitude parity data and the second error magnitude parity data are read from the second parity chip.
7. The memory controller of claim 1 , wherein the parity check matrix includes a first parity sub matrix, a second parity sub matrix and a third parity sub matrix.
8. The memory controller of claim 7 , wherein
the second parity sub matrix includes a plurality of unit sub matrixes and a plurality of first zero sub matrixes, each of the plurality of unit sub matrixes and the plurality of first zero sub matrixes having p×p elements, the plurality of unit sub matrixes and the plurality of first zero sub matrixes being alternatingly arranged, and p being a natural number greater than one;
the third parity sub matrix includes a plurality of second zero sub matrixes and a plurality of first offset sub matrixes, each of the plurality of second zero sub matrixes and the plurality of first offset sub matrixes having p×p elements, the plurality of second zero sub matrixes and the plurality of first offset sub matrixes being alternatingly arranged;
the first parity sub matrix includes a plurality of second offset sub matrixes and two third zero sub matrixes, the plurality of second offset sub matrixes being different from one another and corresponding to a plurality of data chips included in the memory module; and
the first portion of the parity check matrix includes the second parity sub matrix and the third parity sub matrix.
9. The memory controller of claim 8 , wherein the processing circuitry is configured to:
generate the first syndrome by performing a matrix-multiplication operation on the read codeword and the second parity sub matrix;
generate the second syndrome by performing a matrix-multiplication operation on the read codeword and the third parity sub matrix; and
generate the decision syndrome by summing the first syndrome and the second syndrome.
10. The memory controller of claim 9 , wherein the processing circuitry is configured to generate a third syndrome indicating a position of a correctable error by performing a matrix-multiplication operation on the read codeword and the first parity sub matrix in response to the decision syndrome having a non-zero logic level.
11. The memory controller of claim 1 , wherein the processing circuitry is configured to:
perform ECC encoding on a user data set and meta data to generate error locator parity data, first error magnitude parity data and second error magnitude parity data using a parity generation matrix; and
output an output codeword to the memory module, the output codeword including the user data set, the meta data, the error locator parity data, the first error magnitude parity data and the second error magnitude parity data.
12. The memory controller of claim 11 , wherein the parity generation matrix includes a first parity sub matrix, a second parity sub matrix and a third parity sub matrix.
13. The memory controller of claim 12 , wherein the processing circuitry is configured to:
generate the error locator parity data by performing ECC encoding on the user data set and the meta data using the first parity sub matrix;
generate the first error magnitude parity data by performing a matrix-multiplication operation on the second parity sub matrix, the user data set, the meta data and the error locator parity data; and
generate the second error magnitude parity data by performing a matrix-multiplication operation on the third parity sub matrix, the user data set, the meta data and the error locator parity data.
14. The memory controller of claim 12 , wherein
the second parity sub matrix includes a plurality of unit sub matrixes and a plurality of first zero sub matrixes, each of the plurality of unit sub matrixes and the plurality of first zero sub matrixes having p×p elements, the plurality of unit sub matrixes and the plurality of first zero sub matrixes being alternatingly arranged, and p being a natural number greater than one;
the third parity sub matrix includes a plurality of second zero sub matrixes and a plurality of first offset sub matrixes, each of the plurality of second zero sub matrixes and the plurality of first offset sub matrixes having p×p elements, the plurality of second zero sub matrixes and the plurality of first offset sub matrixes being alternatingly repeated; and
the first parity sub matrix includes a plurality of second offset sub matrixes and two third zero sub matrixes, the plurality of second offset sub matrixes being different from one another and corresponding to a plurality of data chips included in the memory module.
15. A memory system comprising:
a memory module; and
a memory controller including processing circuitry, the processing circuitry configured to,
perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome,
determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome, and
output a decoding status flag indicating the type of error.
16. The memory system of claim 15 , wherein the processing circuitry is configured to:
output the decoding status flag indicating that a user data set of the read codeword includes a correctable error in response to the decision syndrome having a non-zero logic level;
generate a third syndrome indicating a position of the correctable error based on a second portion of the parity check matrix and the read codeword; and
correct the correctable error using the third syndrome to obtain a corrected user data set.
17. The memory system of claim 15 , wherein the processing circuitry is configured to output the decoding status flag indicating that a user data set of the read codeword does not include errors in response to the decision syndrome having a zero logic level and the second syndrome having a zero logic level.
18. The memory system of claim 15 , wherein the processing circuitry is configured to output the decoding status flag indicating that a user data set of the read codeword includes uncorrectable errors in response to the decision syndrome having a zero logic level and the second syndrome having a non-zero logic level.
19. The memory system of claim 15 , wherein
the parity check matrix includes a first parity sub matrix, a second parity sub matrix and a third parity sub matrix;
the second parity sub matrix includes a plurality of unit sub matrixes and a plurality of first zero sub matrixes, each of the plurality of unit sub matrixes and the plurality of first zero sub matrixes having p×p elements, the plurality of unit sub matrixes and the plurality of first zero sub matrixes being alternatingly arranged, and p being a natural number greater than one;
the third parity sub matrix includes a plurality of second zero sub matrixes and a plurality of first offset sub matrixes, each of the plurality of second zero sub matrixes and the plurality of first offset sub matrixes having p×p elements, the plurality of second zero sub matrixes and the plurality of first offset sub matrixes being alternatingly arranged;
the first parity sub matrix includes a plurality of second offset sub matrixes and two third zero sub matrixes, the plurality of second offset sub matrixes being different from one another and corresponding to a plurality of data chips included in the memory module; and
the first portion of the parity check matrix includes the second parity sub matrix and the third parity sub matrix.
20. A memory controller configured to control a memory module, the memory controller comprising:
processing circuitry configured to,
perform ECC encoding on a user data set and meta data to generate error locator parity data, first error magnitude parity data and second error magnitude parity data using a parity generation matrix,
output an output codeword to the memory module, the output codeword including the user data set, the meta data, the error locator parity data, the first error magnitude parity data and the second error magnitude parity data,
perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome,
determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome, and
output a decoding status flag indicating the type of error.