Granted Patent B2

US 12,699,629 · App. 18/504,316 · Granted Aug 4, 2026

Inventors: Sujeet Ayyapureddi (Boise, ID); Scott E. Smith (Boise, ID)

Assignee: Micron Technology, Inc.

G06F11/1068G06F11/1016G06F11/1024G06F11/1048

Abstract

Claims (36)

1 . A method comprising:

writing a value to a mode register of a memory device to set the memory device in a first mode or a second mode;

writing data to a memory array of the memory device;

accessing a first percentage of the memory array in the first mode or a second percentage of the memory array in the second mode; and

writing a same number of bits of data to the memory array when accessing the first percentage of the memory array in the first mode or when accessing the second percentage of the memory array in the second mode.

2 . The method of claim 1 , wherein the first mode and the second mode are both ×4 modes of the memory device.

3 . The method of claim 1 , further comprising:

generating column address associated with one of a first range of column select values in the first mode or associated with one of a second range of column select values in the second mode, wherein the second range is smaller than the first range; and

providing the column address as part of writing the data to the memory array.

4 . The method of claim 1 , further comprising writing the data to the memory array with a different latency in the first mode than in the second mode.

5 . The method of claim 1 , wherein the memory accesses more data within the array to perform a write operation in the first mode as compared with the second mode.

6 . A method comprising:

writing a value to a mode register of a memory device to set an error correction code (BCC) mode of the memory device to one of a first mode or a second mode;

accessing a first percentage of addresses of the memory array of the memory device to store data when the ECC is in the first mode;

accessing a second percentage of addresses of the memory array of the memory device to store data when the ECC is in the second mode, wherein the first percentage is greater than the second percentage; and

accessing the memory array one time to write the data in both the first mode and the second mode.

7 . The method of claim 6 , wherein the first mode and the second mode are both ×4 modes of the memory device.

8 . The method of claim 6 , further comprising writing 64 bits of data to the memory array in the first and the second modes.

9 . The method of claim 6 , wherein a third percentage of addresses are set aside for storage of ECC parity data, wherein the third percentage is based on a difference between the first percentage and the second percentage.

10 . The method of claim 6 , wherein the first mode represents a single error correction ECC mode and the second mode represents a single error correction, double error detection (SECDED) ECC mode.

11 . A method comprising:

writing a value to a mode register of a memory device to set the memory device in a first mode or a second mode;

reading data from a memory array of the memory device;

receiving a signal from the memory device that indicates single bit error correction in the data when the memory device is in the first mode and double bit error detection in the data when the memory device is in the second mode;

addressing a first percentage of the memory array in the first mode; and

addressing a second percentage of the memory array in the second mode.

12 . The method of claim 11 , further comprising writing data to the memory array with a different latency between the first and second modes.

13 . A system comprising:

a memory device comprising:

a mode register configured to store a value, wherein based on the value the memory device operates in a first mode or a second mode;

a memory bank comprising a first plurality of column planes, a second plurality of column planes, and an extra column plane; and

a column decoder configured to store data in a selected one of the first or the second plurality of column planes and parity bits in the extra column plane as part of an access operation in the first mode and configured to store the data in a selected one of the first or the second plurality of column planes, store the parity bits in at least one of non-selected ones of the first or the second plurality of column planes or in the extra column plane as part of the second mode; and

a controller configured to write the value to the mode register to set the memory in the first mode or the second mode, wherein the controller is configured to write data to the memory device with a different amount of latency in the first mode as compared with the second mode.

14 . The system of claim 13 , wherein the memory device further comprises an error correction code (ECC) circuit configured to operate in a single error correction scheme in the first mode and in a single error correction double error detection scheme in the second mode.

15 . The system of claim 13 , wherein the memory device comprises a plurality of data terminals, and wherein the controller is configured to send and receive data through four of the plurality of data terminals.

16 . The system of claim 13 , wherein the controller is configured to generate a column address as part of a write operation, wherein the column address is generated to be associated with a first range of column select values when the memory device is in the first mode and a second range of column select values when the memory device is in the second mode.

Assignments (1)

Continuity (2)

References Cited (259)