IP Library › Granted Patent US 12,204,770
Granted Patent B2
US 12,204,770 · App. 17/730,992 · Granted Jan 21, 2025

Apparatuses, systems, and methods for managing metadata security and access

Inventor: Sujeet Ayyapureddi (Boise, ID)
Assignee: Micron Technology, Inc.
G06F3/0622G06F3/0655G06F3/0679G06F13/1668
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Quick Facts
Patent No.
US 12,204,770
App. No.
17/730,992
Granted
Jan 21, 2025
Kind
B2
Abstract

Apparatuses, systems, and methods for managing access to metadata stored at a memory. To manage access to metadata, a mode register is configured to receive a metadata enable setting and to provide a metadata enable signal based on the metadata enable setting. A metadata access control circuit configured to receive a column address identifying a particular column to be accessed within a memory array. The metadata access control circuit blocks access to a column corresponding to the column address when the column address matches one of a plurality of particular column addresses designated for storage of metadata and the metadata enable signal has a first value, and permits access to a column corresponding to the column address when the column address is different than every one of the a plurality of particular column addresses designated for storage of metadata or the metadata enable signal has a second value.

Claims (50)

1. An apparatus comprising:

a memory array;

a mode register configured to provide a metadata enable signal indicating whether a metadata storage feature is enabled; and

a column decoder, configured to, during an access operation, receive a column address identifying a particular column to be accessed within the memory array and the metadata enable signal; wherein, when the metadata enable signal indicates that the metadata storage feature is enabled, the column decoder is configured to block access to a column corresponding to the column address when the column address matches a particular column address designated for storage of metadata and wherein the column decoder comprises a metadata access control circuit configured to determine whether access to the column address should be blocked based on the column address and the metadata enable signal.

2. The apparatus of claim 1 , wherein the column decoder is configured to determine a plurality of column addresses designated for storage of metadata, including the particular column address.

3. The apparatus of claim 1 , wherein the metadata access control circuit comprises a comparator configured to compare the column address to the particular column address to detect whether the column address matches a particular column address.

4. The apparatus of claim 3 , wherein the metadata access control circuit comprises a NAND logic gate configured to apply NAND logic to the output of the comparator and the metadata enable signal to block access to the column address.

5. The apparatus of claim 1 , wherein the mode register is configured to set the metadata enable signal based on a command received from a controller.

6. An apparatus comprising:

a memory array;

a mode register configured to provide a metadata enable signal indicating whether a metadata storage feature is enabled; and

a column decoder, configured to, during an access operation, receive a column address identifying a particular column to be accessed within the memory array and the metadata enable signal; wherein, when the metadata enable signal indicates that the metadata storage feature is enabled, the column decoder is configured to block access to a column corresponding to the column address when the column address matches a particular column address designated for storage of metadata and wherein the mode register is configured to set the metadata enable signal based on a metadata fuse setting.

7. The apparatus of claim 6 , further comprising the fuse configured to indicate whether the metadata feature is enabled.

8. An apparatus comprising:

a memory array;

a mode register configured to provide a metadata enable signal indicating whether a metadata storage feature is enabled; and

a column decoder, configured to, during an access operation, receive a column address identifying a particular column to be accessed within the memory array and the metadata enable signal; wherein, when the metadata enable signal indicates that the metadata storage feature is enabled, the column decoder is configured to block access to a column corresponding to the column address when the column address matches a particular column address designated for storage of metadata and wherein the column decoder is configured to, when the metadata enable signal indicates that the metadata storage feature is enabled, prevent activation of a column select signal corresponding to the column associated with the column address when the column address matches a particular column address designated for storage of metadata.

9. An apparatus comprising:

a memory array;

a mode register configured to provide a metadata enable signal indicating whether a metadata storage feature is enabled; and

a column decoder, configured to, during an access operation, receive a column address identifying a particular column to be accessed within the memory array and the metadata enable signal; wherein, when the metadata enable signal indicates that the metadata storage feature is enabled, the column decoder is configured to block access to a column corresponding to the column address when the column address matches a particular column address designated for storage of metadata and wherein the column decoder is configured to allow access to the column corresponding to the column address when the metadata enable signal indicates that the metadata storage feature is disabled or when the column associated with the column address when the column address is different than every column address designated for storage of metadata.

10. An apparatus comprising:

a mode register configured to receive a metadata enable setting and to provide a metadata enable signal based on the metadata enable setting; and

a metadata access control circuit configured to receive the metadata enable setting and a column address identifying a particular column to be accessed within a memory array, wherein the metadata access control circuit is configured to block access to a column corresponding to the column address when the column address matches one of a plurality of particular column addresses designated for storage of metadata and the metadata enable signal has a first value, wherein the metadata access control circuit is configured to permit access to a column corresponding to the column address when the column address is different than every one of the a plurality of particular column addresses designated for storage of metadata or the metadata enable signal has a second value.

11. The apparatus of claim 10 , further comprising a column decoder configured to determine the plurality of particular column addresses designated for storage of metadata.

12. The apparatus of claim 10 , wherein the metadata access control circuit comprises a comparator configured to compare the column address to each of the plurality of particular column addresses designated for storage of metadata to detect a match.

13. The apparatus of claim 10 , wherein the mode register is configured to receive the metadata enable setting from a controller.

14. The apparatus of claim 10 , wherein the mode register is configured to receive the metadata enable setting from a metadata enable fuse setting.

15. A method comprising:

receiving, during an access operation at a semiconductor device, a column address identifying a particular column to be accessed within a memory array of the semiconductor device;

receiving a metadata enable signal from a mode register of the semiconductor device;

when the metadata enable signal indicates that the metadata storage feature is enabled, blocking access to a column corresponding to the column address when the column address matches a particular column address designated for storage of metadata memory array; and

comparing the column address to the particular column address via a comparator circuit to detect whether the column address matches the particular column address.

16. The method of claim 15 , further comprising determining a plurality of column addresses designated for storage of metadata, including the particular column address.

17. The method of claim 15 , further comprising setting the metadata enable signal based on a command received from a controller.

18. A method comprising:

receiving, during an access operation at a semiconductor device, a column address identifying a particular column to be accessed within a memory array of the semiconductor device;

setting a metadata enable signal based on a metadata fuse setting;

receiving the metadata enable signal from a mode register of the semiconductor device; and

when the metadata enable signal indicates that the metadata storage feature is enabled, blocking access to a column corresponding to the column address when the column address matches a particular column address designated for storage of metadata memory array.

19. The method of claim 18 , further comprising blowing the fuse configured to disable the metadata feature.

20. A method comprising:

receiving, during an access operation at a semiconductor device, a column address identifying a particular column to be accessed within a memory array of the semiconductor device;

receiving a metadata enable signal from a mode register of the semiconductor device; and

when the metadata enable signal indicates that the metadata storage feature is enabled, blocking access to a column corresponding to the column address when the column address matches a particular column address designated for storage of metadata memory array and preventing activation of a column select signal corresponding to the column associated with the column address when the column address matches a particular column address designated for storage of metadata.

21. A method comprising:

receiving, during an access operation at a semiconductor device, a column address identifying a particular column to be accessed within a memory array of the semiconductor device;

receiving a metadata enable signal from a mode register of the semiconductor device;

when the metadata enable signal indicates that the metadata storage feature is enabled, blocking access to a column corresponding to the column address when the column address matches a particular column address designated for storage of metadata memory array; and

permitting access to the column corresponding to the column address when the metadata enable signal indicates that the metadata storage feature is disabled or when the column associated with the column address when the column address is different than every column address designated for storage of metadata.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2022
From: AYYAPUREDDI, SUJEET
To: MICRON TECHNOLOGY, INC.
Reel/Frame 059743/0836 →
Continuity (1)
Related Publication 20230350581A1 · Nov 2, 2023
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