Apparatuses and methods for single-pass access of ECC information, metadata information or combinations thereof
Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.
1 . An apparatus comprising:
a memory bank comprising:
a first data column plane comprising a first bit line and a second bit line;
a second data column plane comprising a third bit line and a fourth bit line, and
an extra column plane comprising a fifth bit line and a sixth bit line;
a column decoder configured to activate the first bit line, the fourth bit line, and the fifth bit line as part of an access operation; and
an error correction code (ECC) circuit configured to access a data bit along the first bit line, a metadata bit along the fifth bit line, and a parity bit along the fourth bit line as part of the access operation, wherein a parity bit stored along the second bit line is associated with a data in data bit stored along the third bit line, and wherein the data bit along the first bit line is associated with the parity bit stored along the fourth bit line.
2 . The apparatus of claim 1 , wherein the column decoder is configured to activate the second bit line, the third bit line and the fifth bit line as part of a second access operation, wherein the ECC circuit is configured to access data along the third bit line, parity bits along the second bit line, and metadata along the sixth bit line as part of the second access operation.
3 . The apparatus of claim 1 , wherein the column decoder is configured to selectively activate the bit lines based on a received column address, and wherein the column address includes a column plane select bit which specifies if the data is stored in the first data column plane or the second data column plane.
4 . The apparatus of claim 1 , further comprising an input/output circuit configured to receive the data and the metadata from the ECC circuit if the access operation is a read operation and configured to provide the data and the metadata to the ECC circuit if the access operation is a write operation.
5 . The apparatus of claim 1 , wherein the ECC circuit is configured to locate and correct errors in the data and the metadata based on the data metadata and the parity when the access operation is a read operation.
6 . The apparatus of claim 1 , wherein responsive to a column address received as part of the access operation the column decoder is configured to provide a column select signal with a first value to the first data column plane, a second column select signal with a second value to the second data column plane and a third column select signal with the first value to the extra column plane.
7 . An apparatus comprising:
a memory bank comprising:
a first plurality of column planes;
a second plurality of column planes; and
an extra column plane; and
a column decoder configured to select the first or the second plurality of column planes based on a column address received as part of an access operation, wherein as part of the access operation data bits are accessed in the selected one of the first or the second plurality of column planes, parity bits are accessed in the non-selected one of the first or the second plurality of column planes, and metadata bits are accessed in the extra column plane,
wherein the column address includes a column plane select bit and wherein the first plurality of column planes or the second plurality of column planes is selected based on the column plane select bit,
wherein a plurality of bits are accessed from the extra column plane and wherein the column decoder selects a first half or a second half of the plurality of bits as the metadata bits.
8 . The apparatus of claim 7 , further comprising an error correction code (ECC) circuit configured to locate and correct errors in the data bits and the metadata bits based on the parity bits when the access operation is a read operation.
9 . The apparatus of claim 8 , wherein the ECC circuit is configured to perform single error correction double error detection (SECDED).
10 . The apparatus of claim 7 , wherein the apparatus is a memory device operating in an ×4 mode.
11 . An apparatus comprising:
a memory bank comprising:
a first plurality of column planes;
a second plurality of column planes; and
an extra column plane:
a column decoder configured to select the first or the second plurality of column lanes based on a column address received as part of an access operation, wherein as part of the access operation data bits are accessed in the selected one of the first or the second plurality of column planes, parity bits are accessed in the non-selected one of the first or the second plurality of column planes, and metadata bits are accessed in the extra column plane;
a first plurality of local input/output (LIO) lines coupled to the first plurality of column planes; and
a second plurality of LIO lines coupled to the second plurality of column planes, wherein the column decoder is configured to activate all of the first plurality or the second plurality of LIO lines coupled to the selected one of the first or the second plurality of column planes and less than all of the first plurality or the second plurality of LIO lines coupled to the non-selected one of the first or the second plurality of column planes as part of the access operation.