Programmable capacitor memory arrays with stacked access transistors
Bits are stored in an array with multiple capacitors per access transistor. An array of multiple ferroelectric capacitors shares a nanowire or nanosheet as a common plate and stores information accessed by a single common select transistor, which uses the nanowire or nanosheet for its channel. In an integrated circuit (IC) system, a group of bitlines is connected to a capacitor array by arrays of nanowires or nanosheets and wordline-controlled non-planar transistors. An IC die with a capacitor array accessed by a single select transistor and sharing a nanowire or nanosheet is coupled to a power supply and a cooling structure.
1 . An apparatus, comprising:
an array of continuous nanowires or nanosheets, wherein individual ones of the continuous nanowires or nanosheets comprise a transistor channel region of the continuous nanowires or nanosheets and a first capacitor plate region of the continuous nanowires or nanosheets;
an array of gate structures, wherein individual ones of the gate structures are in contact with corresponding ones of the transistor channel regions;
a plurality of bitlines extending in a first direction, wherein individual ones of the bitlines are coupled to first ends of the transistor channel regions, and second ends of the transistor channel regions are immediately adjacent to corresponding ones of the first capacitor plate regions;
a plurality of wordlines extending in a second direction substantially orthogonal to the first direction, wherein individual ones of the wordlines are coupled to the gate structures; and
an array of capacitors, wherein individual ones of the capacitors comprise a portion of corresponding ones of the first capacitor plate regions, a ferroelectric material surrounding the portion of the first capacitor plate regions, and a second capacitor plate surrounding the ferroelectric material.
2 . The apparatus of claim 1 , further comprising a plurality of platelines, wherein individual ones of the platelines are coupled to a plurality of the second capacitor plates.
3 . The apparatus of claim 2 , wherein the platelines are substantially parallel to the bitlines.
4 . The apparatus of claim 2 , wherein the platelines are substantially parallel to the wordlines.
5 . The apparatus of claim 2 , wherein the platelines extend in a third direction substantially orthogonal to both the first direction and the second direction.
6 . The apparatus of claim 1 , wherein the ferroelectric material comprises oxygen and one of hafnium, zirconium, or niobium.
7 . The apparatus of claim 1 , wherein individual ones of the gate structures comprise tungsten, cobalt, molybdenum, ruthenium, or both nitrogen and either titanium or tantalum.
8 . The apparatus of claim 1 , wherein the continuous nanowires or nanosheets each comprise a dopant and the first capacitor plate regions have a concentration of the dopant greater than a concentration of the dopant in the transistor channel regions.
9 . The apparatus of claim 1 , wherein the continuous nanowires or nanosheets each have a thickness of not more than 2 nm.
10 . The apparatus of claim 1 , wherein a thickness of the ferroelectric material is not more than 7 nm.
11 . The apparatus of claim 1 , comprising:
a power supply; and
an integrated circuit (IC) die coupled to the power supply, the IC die comprising the array of continuous nanowires or nanosheets, the array of gate structures, the plurality of bitlines, the plurality of wordlines, and the array of capacitors.
12 . The apparatus of claim 11 , comprising:
a cooling structure thermally coupled to the IC die, the cooling structure operable to remove heat from the IC die to achieve an operating temperature of not more than −25° C.
13 . An apparatus, comprising:
a plurality of capacitors comprising a shared inner plate, wherein individual ones of the capacitors comprise an outer plate and a ferroelectric material between the shared inner plate and the outer plate;
a transistor comprising a channel portion; and
a continuous nanowire or nanosheet comprising the channel portion and the shared inner plate, wherein the ferroelectric material surrounds the shared inner plate and the outer plate surrounds the ferroelectric material.
14 . The apparatus of claim 13 , comprising:
a bitline extending in a first direction and coupled to a first end of the channel portion;
a wordline extending in a second direction substantially orthogonal to the first direction, the wordline coupled to a gate structure of the transistor; and
a plateline coupled to the outer plate.
15 . The apparatus of claim 14 , wherein the plateline is substantially parallel to the bitline.
16 . The apparatus of claim 14 , wherein the plateline is substantially parallel to the wordline.
17 . The apparatus of claim 14 , wherein the plateline extends in a third direction substantially orthogonal to both the first direction and the second direction.
18 . The apparatus of claim 13 , wherein the ferroelectric material comprises oxygen and one of hafnium, zirconium, or niobium, and wherein a gate structure of the transistor comprises tungsten, cobalt, molybdenum, ruthenium, or both nitrogen and either titanium or tantalum.
19 . The apparatus of claim 13 , wherein the continuous nanowire or nanosheet comprises a dopant and the shared inner plate has a concentration of the dopant greater than a concentration of the dopant in the channel portion.
20 . The apparatus of claim 13 , wherein the continuous nanowire or nanosheet has a thickness of not more than 2 nm.
21 . The apparatus of claim 13 , wherein a thickness of the ferroelectric material is not more than 7 nm.
22 . The apparatus of claim 13 , comprising:
a power supply; and
an integrated circuit (IC) die coupled to the power supply, the IC die comprising the plurality of capacitors, the transistor, and the continuous nanowire or nanosheet.
23 . The apparatus of claim 22 , comprising:
a cooling structure thermally coupled to the IC die, the cooling structure operable to remove heat from the IC die to achieve an operating temperature of not more than −25° C.