Semiconductor packages for stacked memory-on-package (SMOP) and methods of manufacturing the same
A semiconductor package includes a package substrate, a base die including a first die surface coupled to the package substrate, and a second die surface opposite to the first die surface, and a first device including a first device surface coupled to the package substrate, and a second device surface opposite to the first device surface. The semiconductor package further includes a second device including a third device surface coupled to the second device surface, and a fourth device surface opposite to the third device surface, and a bridge including a first portion coupled to the package substrate, and a second portion coupled to the first portion, the fourth device surface and the second die surface.
1 . A semiconductor package comprising:
a package substrate;
a base die comprising a first die surface coupled to the package substrate, and a second die surface opposite to the first die surface;
a first device comprising a first device surface coupled to the package substrate, and a second device surface opposite to the first device surface;
a second device comprising a third device surface coupled to the second device surface, and a fourth device surface opposite to the third device surface; and
a bridge comprising a first portion coupled to the package substrate, and a second portion coupled to the first portion, the fourth device surface and the second die surface.
2 . The semiconductor package of claim 1 , wherein the first portion comprises one or more first conductive planes having a first thickness ranging from 50 μm to 500 μm,
wherein the second portion comprises a metal redistribution layer (RDL) coupled to the one or more first conductive planes, the fourth device surface and the second die surface, and one or more second conductive planes having a second thickness ranging from 2 μm to 30 μm.
3 . The semiconductor package of claim 2 , wherein the one or more first and second conductive planes comprises:
at least one power conductive plane associated to a power supply voltage; and
at least one ground conductive plane associated to a ground reference voltage.
4 . The semiconductor package of claim 2 , wherein the second portion further comprises a silicon or organic substrate on which the metal RDL is disposed.
5 . The semiconductor package of claim 2 , wherein the first portion further comprises one or more epoxy mold layers interposed between the package substrate and the second portion of the bridge,
wherein the one or more first conductive planes are disposed through the one or more epoxy mold layers.
6 . The semiconductor package of claim 5 , wherein the second portion comprises an epoxy mold layer so that the second portion and the first portion are integrally formed.
7 . The semiconductor package of claim 1 , wherein the second portion of the bridge extends at least partially over the first device, the second device and the base die.
8 . The semiconductor package of claim 1 , further comprising one or more chiplets disposed on the second die surface, and coupled to the second device through the second portion of the bridge.
9 . The semiconductor package of claim 8 , wherein each of the one or more chiplets comprises one among a central processing unit, a graphic processing unit, a system-on-chip, a radio frequency integrated circuit, a deep learning processor, a neural network processor and an input/output tile.
10 . The semiconductor package of claim 1 , wherein each of the first device and the second device comprises a memory device.
11 . A computing device comprising:
a semiconductor package comprising:
a package substrate;
a base die comprising a first die surface coupled to the package substrate, and a second die surface opposite to the first die surface;
a first device comprising a first device surface coupled to the package substrate, and a second device surface opposite to the first device surface;
a second device comprising a third device surface coupled to the second device surface, and a fourth device surface opposite to the third device surface; and
a bridge comprising a first portion and a second portion coupled to the first portion, the fourth device surface and the second die surface, wherein the first portion comprises one or more first conductive planes interposed between the package substrate and the second portion of the bridge, and coupled to a metal redistribution layer (RDL) having one or more second conductive planes in the second portion of the bridge.
12 . The computing device of claim 11 , wherein the bridge comprises:
a silicon or organic substrate; and
the RDL is disposed on the silicon or organic substrate, and coupled to the one or more first conductive planes, the fourth device surface and the second die surface.
13 . The computing device of claim 11 , wherein the one or more first and second conductive planes comprises:
at least one power conductive plane associated to a power supply voltage; and
at least one ground conductive plane associated to a ground reference voltage.
14 . The computing device of claim 11 , wherein the first portion further comprises one or more epoxy mold layers interposed between the package substrate and the second portion of the bridge,
wherein the one or more first conductive planes are disposed through the one or more epoxy mold layers.
15 . The computing device of claim 11 , further comprising one or more chiplets disposed on the second die surface, and coupled to the second device through the second portion of the bridge.