NAND string utilizing floating body memory cell
NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.
1. A semiconductor memory array comprising:
a plurality of NAND string configurations, each said NAND string configuration comprising:
a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;
a select gate drain device connected at one end of said string of semiconductor memory cells, wherein said select gate drain device is not a semiconductor memory cell; and
a select gate source device connected at an opposite end from said one end of said string of semiconductor memory cells, wherein said select gate source device is not a semiconductor memory device;
wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a third region in electrical contact with said floating body region and spaced apart from said first and second regions;
wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region;
wherein said third region is commonly connected to at least two of said semiconductor memory cells;
wherein each said at least one of said plurality of semiconductor memory cells has only one gate;
wherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals;
wherein said select gate drain device is connected to a local bit line; and
at least one transistor isolating said local bit line from a primary bit line.
2. The semiconductor memory array of claim 1 , wherein each said NAND string configuration is configured to perform at least one of: injecting charge into or extracting charge out of a portion of at least one of said semiconductor memory cells to maintain a state of said at least one of said semiconductor memory cells.
3. The semiconductor memory array of claim 1 , wherein said third region is configured to perform at least one of injecting charge into or extracting charge out of at least a portion of said floating body region.
4. The semiconductor memory array of claim 1 , wherein said floating body region is provided in a fin structure that extends vertically above said third region.
5. The semiconductor memory array of claim 1 , wherein a constant voltage bias is applied to said third region.
6. The semiconductor memory array of claim 1 , wherein a periodic pulse of voltage is applied to said third region.
7. An integrated circuit comprising:
a semiconductor memory array comprising:
a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;
a select gate drain device connected at one end of said string of semiconductor memory cells, wherein said select gate drain device is not a semiconductor memory cell; and
a select gate source device connected at an opposite end of said string of semiconductor memory cells, wherein said select gate source device is not a semiconductor memory device;
wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a third region in electrical contact with said floating body region and spaced apart from said first and second regions;
wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said semiconductor memory cell;
wherein each of said at least one of said plurality of semiconductor memory cells has only one gate;
wherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals;
wherein said select gate drain device is connected to a local bit line;
at least one transistor isolating said local bit line from a primary bit line; and
a control circuit configured to provide electrical signals to said local bit line and said primary bit line.
8. The integrated circuit of claim 7 , wherein said string of semiconductor memory cells is configured to perform at least one of: injecting charge into or extracting charge out of a portion of at least one of said semiconductor memory cells to maintain a state of said at least one semiconductor memory cell.
9. The integrated circuit of claim 7 , wherein said third region is configured to perform said at least one of injecting charge into or extracting charge out of at least a portion of said floating body region.
10. The integrated circuit of claim 7 , wherein said floating body region is provided in a fin structure that extends vertically above said third region.
11. The integrated circuit of claim 7 , wherein a constant voltage bias is applied to said third region.
12. The integrated circuit of claim 7 , wherein a periodic pulse of voltage is applied to said third region.
13. A semiconductor memory array comprising:
a plurality of NAND string configurations, each said NAND string configuration comprising:
a plurality of semiconductor memory cells serially connected to one another to form a string of semiconductor memory cells;
a select gate drain device connected at one end of said string of semiconductor memory cells, wherein said select gate drain device is not a semiconductor memory cell; and
a select gate source device connected at an opposite end of said string of semiconductor memory cells, wherein said select gate source device is not a semiconductor memory device;
wherein at least one of said plurality of semiconductor memory cells each comprise a substrate and a floating body region formed as part of said substrate and configured to store data as charge therein to define a state of said semiconductor memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a third region in electrical contact with said floating body region and spaced apart from said first and second regions;
wherein said third region is configured to function as a collector region to maintain a charge of said floating body region, thereby maintaining said state of said floating body region;
wherein said third region is commonly connected to at least two of said semiconductor memory cells;
wherein each said at least one of said plurality of semiconductor memory cells has only one gate;
wherein serial connections between at least two of said semiconductor memory cells are not connected to any terminals;
wherein said select gate source device is connected to a local source line; and
at least one transistor isolating said local source line from a primary source line.
14. The semiconductor memory array of claim 13 , wherein each said NAND string configuration is configured to perform at least one of: injecting charge into or extracting charge out of a portion of at least one of said semiconductor memory cells to maintain a state of said at least one semiconductor memory cell.
15. The semiconductor memory array of claim 13 , wherein said third region is configured to perform said at least one of injecting charge into or extracting charge out of at least a portion of said floating body region.
16. The semiconductor memory array of claim 13 , wherein said floating body region is provided in a fin structure that extends vertically above said third region.
17. The semiconductor memory array of claim 13 , wherein a constant voltage bias is applied to said third region.
18. The semiconductor memory array of claim 13 , wherein a periodic pulse of voltage is applied to said third region.