Unipolar programming of memory cells
Systems, methods, and apparatuses are provided for unipolar programming of memory cells in a semiconductor device. A memory has a plurality of self-selecting memory cells and circuitry configured to program a self-selecting memory cell of the plurality of self-selecting memory cells to a first data state or a second data state by applying a current pulse to the self-selecting memory cell. The current is a set pulse or a reset pulse. The set pulse and the reset pulse have a same polarity.
1. An apparatus, comprising:
a memory having a plurality of memory tiles, wherein:
each of the plurality of memory tiles includes a plurality of memory planes; and
a plurality of self-selecting memory cells are included in each of the plurality of memory planes; and
circuitry configured to concurrently program a first self-selecting memory cell of the plurality of self-selecting memory cells to a first data state or a second data state by applying a first current pulse to the first self-selecting memory cell and program a second self-selecting memory cell of the plurality of self-selecting memory cells to the other of the first data state or the second data state by applying a second current pulse to the second self-selecting memory cell, wherein:
the first current pulse is a set pulse or a reset pulse and the second current pulse is the other of the set pulse or the reset pulse;
the set pulse and the reset pulse have a negative polarity;
the first data state is a different data state than the second state; and
the first current pulse and the second current pulse are applied concurrently.
2. The apparatus of claim 1 , wherein a duration of the set pulse is greater than or equal to a duration of the reset pulse.
3. The apparatus of claim 1 , wherein the set pulse has a lower magnitude than the reset pulse.
4. The apparatus of claim 1 , wherein the circuitry is configured to:
program the first self-selecting memory cell or the second self-selecting memory cell to the first data state by applying the set pulse to the first self-selecting memory cell or the second self-selecting memory cell; and
program the first self-selecting memory cell or the second self-selecting memory cell to the second data state by applying the reset pulse to the first self-selecting memory cell or the second self-selecting memory cell.
5. The apparatus of claim 1 , wherein the first self-selecting memory cell and the second self-selecting memory cell are programmed to the first data state or the second data state based on a magnitude of the first current pulse or the second current pulse.
6. The apparatus of claim 5 , wherein the first self-selecting memory cell and the second self-selecting memory cell are programmed to the first data state when the magnitude of the first current pulse or the second current pulse is below a threshold magnitude.
7. The apparatus of claim 5 , wherein the first self-selecting memory cell and the second self-selecting memory cell are programmed to the second data state when the magnitude of the first current pulse or the second current pulse is above a threshold magnitude.
8. An apparatus, comprising:
a memory having a plurality of self-selecting memory cells; and
circuitry configured to concurrently program a first self-selecting memory cell of the plurality of self-selecting memory cells in a memory tile to one of a first data state and a second data state and program a second self-selecting memory cell of the plurality of self-selecting memory cells in the memory tile to the other one of the first data state and the second data state by concurrently applying a first current pulse to the first self-selecting memory cell and a second current pulse to the second self-selecting memory cell, wherein:
the first current pulse is one of a set pulse and a reset pulse;
the second current pulse is the other one of the set pulse and the reset pulse;
a duration of the set pulse is greater than or equal to a duration of the reset pulse;
the set pulse as a lower magnitude than the reset pulse;
the set pulse and the reset pulse have a negative polarity; and
the first data state is a different data state than the second data state.
9. The apparatus of claim 8 , wherein:
the memory tile includes a plurality of memory planes; and
the plurality of self-selecting memory cells are included in each of the plurality of memory planes.
10. The apparatus of claim 9 , wherein the first self-selecting memory cell and the second self-selecting memory cell are included in a same memory plane of the plurality of memory planes.
11. The apparatus of claim 8 , wherein:
the memory includes a plurality of vertical pillars;
the first self-selecting memory cell is coupled to a first vertical pillar of the plurality of vertical pillars; and
the second self-selecting memory cell is coupled to a second vertical pillar of the plurality of vertical pillars.
12. The apparatus of claim 8 , wherein the first self-selecting memory cell is programmed to the first data state and the second self-selecting memory cell is programmed to the second data state.
13. The apparatus of claim 8 , wherein the first self-selecting memory cell and the second self-selecting memory cell are programmed independently.
14. A method of operating memory, comprising:
programming a first self-selecting memory cell of a particular memory tile to a first data state or a second data state and programming a second self-selecting memory cell of the particular memory tile to the other of the first data state or the second data by:
selecting the first self-selecting memory cell and the second self-selecting memory cell; and
concurrently applying, while the first self-selecting memory cell and the second self-selecting memory cell are selected, a first current pulse to a first vertical pillar that is coupled to the first self-selecting memory cell and a second current pulse to a second vertical pillar that is coupled to the second self-selecting memory cell, wherein:
the first current pulse is one of a set pulse or a reset pulse;
the second current pulse is the other one of the set pulse or the reset pulse;
a duration of the set pulse is greater than or equal to a duration of the reset pulse;
the set pulse has a lower magnitude than the reset pulse;
the set pulse and the reset pulse have a negative polarity; and
the first data state is a different data state than the second data state.
15. The method of claim 14 , further comprising selecting the first self-selecting memory cell by applying the first current to a first horizontal access line coupled to the first self-selecting memory cell and selecting the second self-selecting memory cell by applying the second current to a second horizontal access line coupled to the second self-selecting memory cell.
16. The method of claim 14 , further comprising selecting a polarity of the first self-selecting memory cell and the second self-selecting memory cell before selecting the first self-selecting memory cell and the second self-selecting memory cell.
17. The method of claim 14 , wherein:
the first current pulse is applied to the first vertical pillar via a first current mirror circuit coupled to the first vertical pillar; and
the second current pulse is applied to the second vertical pillar via a second current mirror circuit coupled to the second vertical pillar.
18. The method of claim 17 , wherein:
the first current mirror circuit outputs the first current pulse to the first vertical pillar; and
the second current mirror circuit outputs the second current pulse to the second vertical pillar.
19. A method of operating memory, comprising:
concurrently programming a first self-selecting memory cell to one of a first data state and a second data state and a second self-selecting memory cell to the other one of the first data state and the second data state by:
concurrently selecting the first self-selecting memory cell and the second self-selecting memory cell; and
concurrently applying, while the first self-selecting memory cell and the second self-selecting memory cell are selected, a first current pulse to a first vertical pillar that is coupled to the first self-selecting memory cell and a second current pulse to a second vertical pillar that is coupled to the second self-selecting memory cell, wherein:
the first current pulse is one of a set pulse and a reset pulse;
the second current pulse is the other one of the set pulse and the reset pulse;
a duration of the set pulse is greater than or equal to a duration of the reset pulse;
the set pulse has a lower magnitude than the reset current pulse;
the set pulse and the reset pulse have a negative polarity; and
the first data state is a different data state than the second data state.
20. The method of claim 19 , further comprising performing a program verify operation on the first self-selecting memory cell and the second self-selecting memory cell after programming the first self-selecting memory cell and the second self-selecting memory cell.
21. The method of claim 20 , further comprising performing the program verify operation by:
alternately applying a plurality of first current pulses and a plurality of second current pulses to the first self-selecting memory cell; and
alternately applying the plurality of first current pulses and the plurality of second current pulses to the second self-selecting memory cell.
22. The method of claim 21 , wherein:
the program verify operation increases a threshold voltage of the first self-selecting memory cell when the threshold voltage of the first self-selecting memory cell is below a first selected threshold voltage and above a second selected threshold voltage; and
the program verify operation increases a threshold voltage of the second self-selecting memory cell when the threshold voltage of the second self-selecting memory cell is below a third selected threshold voltage and above a fourth selected threshold voltage.
23. The method of claim 19 , further comprising continuously applying an access line current to access lines coupled to the first vertical pillar and the second vertical pillar.