Gate structures in semiconductor devices
A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.
1. A device comprising:
a semiconductor fin extending above an isolation region;
a high-k gate dielectric layer over and extending along sidewalls of the semiconductor fin, the high-k gate dielectric layer comprising fluorine; and
a gate stack over and along sidewalls of the high-k gate dielectric layer, wherein the gate stack comprises:
a first work function metal layer comprising an n-type metal and fluorine;
a capping layer over the first work function metal layer, wherein the capping layer comprises the n-type metal, and wherein a concentration of the n-type metal in the capping layer decreases in a direction away from the first work function metal layer; and
a first fill metal layer over the capping layer wherein the first fill metal layer is free of fluorine.
2. The device of claim 1 , wherein the gate stack further comprises an adhesion layer between the first work function metal layer and the high-k gate dielectric layer.
3. The device of claim 1 , wherein the gate stack further comprises a barrier layer between the capping layer and the first fill metal layer.
4. The device of claim 1 , wherein the gate stack further comprises a second fill metal layer over the first fill metal layer, wherein the second fill metal layer comprises fluorine.
5. The device of claim 1 , wherein a fluorine concentration of a portion of the high-k gate dielectric layer on a top surface of the semiconductor fin is in a range of 1.0 at % to 40.0 at %, and wherein a fluorine concentration of a portion of the high-k gate dielectric layer on a sidewall of the semiconductor fin is in a range of 1.0 at % to 40.0 at %.
6. The device of claim 1 , wherein a fluorine concentration of a portion of the first work function metal layer on a top surface of the semiconductor fin is in a range of to at % to 40.0 at %, and wherein a fluorine concentration of a portion of the first work function metal layer on a sidewall of the semiconductor fin is in a range of 1.0 at % to 40.0 at %.
7. The device of claim 1 , wherein the capping layer comprises fluorine.
8. The device of claim 1 further comprising a p-type work function metal layer between the first work function metal layer and the high-k gate dielectric layer.
9. The device of claim 1 further comprising an interfacial layer between the high-k gate dielectric layer and the semiconductor fin, wherein the interfacial layer comprises fluorine.
10. The device of claim 1 further comprising an interfacial layer between the high-k gate dielectric layer and the semiconductor fin, wherein the interfacial layer is free of fluorine.
11. A device comprising:
a semiconductor substrate;
a gate dielectric over the semiconductor substrate, wherein the gate dielectric comprises a high-k material and a passivating species, and wherein the passivating species is fluorine or nitrogen;
a gate stack over the gate dielectric, wherein the gate stack comprises:
a work function metal layer comprising aluminum and the passivating species;
a capping layer over the work function metal layer, wherein the capping layer comprises aluminum and the passivating species, wherein a concentration of the aluminum in the capping layer decreases in a direction away from the work function metal layer; and
a fill metal over the capping layer wherein the fill metal is free of the passivating species.
12. The device of claim 11 , wherein the passivating species is fluorine.
13. The device of claim 11 , wherein the passivating species is nitrogen, and wherein the work function metal layer has a greater than stoichiometric composition of nitrogen.
14. The device of claim 11 , wherein a surface of the capping layer opposite to the work function metal layer is free of aluminum.
15. A device comprising:
a semiconductor region;
a high-k gate dielectric layer over and extending along sidewalls of the semiconductor region, the high-k gate dielectric layer comprising fluorine; and
a gate stack over and along sidewalls of the high-k gate dielectric layer, wherein the gate stack comprises:
an n-type work function metal layer comprising aluminum and fluorine;
a capping layer over the n-type work function metal layer, wherein the capping layer comprises aluminum in at least a lower region of the capping layer, and wherein an upper region of the capping layer comprises aluminum at a lower concentration than the lower region of the capping layer;
an adhesion layer over the capping layer; and
a first fill metal over the adhesion layer wherein the first fill metal is free of fluorine.
16. The device of claim 15 further comprising a p-type work function between the n-type work function metal layer and the high-k gate dielectric layer.
17. The device of claim 15 , wherein a surface of the capping layer opposite to the adhesion layer is free of aluminum.
18. The device of claim 15 , further comprising a second fill metal over the first fill metal, wherein the second fill metal comprises fluorine.
19. The device of claim 15 , wherein the n-type work function metal layer and the capping layer each further comprises titanium.
20. The device of claim 15 , wherein the capping layer has a concentration of aluminum that gradually decreases from a bottom surface of the capping layer to a top surface of the capping layer.