Semiconductor device and method

1. A device comprising:

a first source/drain region in a substrate;

a second source/drain region in the substrate;

a first inter-layer dielectric over the first source/drain region and the second source/drain region;

a first source/drain contact extending through the first inter-layer dielectric, the first source/drain contact connected to the first source/drain region, the first source/drain contact having a first width;

a first spacer around the first source/drain contact;

a first void between the first spacer and first sidewalls of the first inter-layer dielectric, the first sidewalls of the first inter-layer dielectric separated by a first distance;

a second source/drain contact extending through the first inter-layer dielectric, the second source/drain contact connected to the second source/drain region, the second source/drain contact having a second width, the second width less than the first width;

a second spacer around the second source/drain contact, the second spacer having a same width as the first spacer; and

a second void between the second spacer and second sidewalls of the first inter-layer dielectric, the second sidewalls of the first inter-layer dielectric separated by a second distance,

wherein a first difference between the first distance and the first width is greater than a second difference between the second distance and the second width.

2. The device of claim 1 , wherein a first height of the first void is different from a second height of the second void.

3. The device of claim 1 , wherein the first void has a greater width than the second void.

4. The device of claim 1 further comprising:

a second inter-layer dielectric over the first inter-layer dielectric, the first source/drain contact and the second source/drain contact extending through the second inter-layer dielectric, the second inter-layer dielectric contacting first sidewalls of the first spacer and second sidewalls of the second spacer.

5. The device of claim 4 , wherein a bottom surface of the second inter-layer dielectric is exposed to the first void and to the second void.

6. The device of claim 4 , wherein the second inter-layer dielectric comprises an impurity having a concentration of in a range of 10 14 cm −3 to 10 16 cm −3 , the impurity comprising Ge, B, Ar, Sn, or Si.

7. A device comprising:

a gate electrode;

a source/drain region adjacent the gate electrode;

a first inter-layer dielectric over the source/drain region;

a second inter-layer dielectric over the first inter-layer dielectric;

a source/drain contact extending through the first inter-layer dielectric and the second inter-layer dielectric, the source/drain contact connected to the source/drain region;

a contact spacer surrounding the source/drain contact, the second inter-layer dielectric contacting a sidewall of the contact spacer; and

a void disposed between the sidewall of the contact spacer and the first inter-layer dielectric, a bottom surface of the second inter-layer dielectric exposed to the void.

8. The device of claim 7 further comprising:

a first spacer disposed between the contact spacer and the first inter-layer dielectric, the first spacer contacting the source/drain region, the void disposed over the first spacer.

9. The device of claim 8 , wherein a first distance between a top surface of the source/drain region and a top surface of the first spacer is less than a second distance between the top surface of the first spacer and a top surface of the gate electrode.

10. The device of claim 7 further comprising:

a first dielectric layer having a first portion and a second portion, the first portion disposed over the second inter-layer dielectric, the contact spacer, and the source/drain contact, the second portion disposed between the sidewall of the contact spacer and the second inter-layer dielectric.

11. The device of claim 7 , wherein the second inter-layer dielectric comprises an impurity having a concentration of in a range of 10 14 cm −3 to 10 16 cm −3 , the impurity comprising Ge, B, Ar, Sn, or Si.

12. A device comprising:

a first source/drain region in a semiconductor substrate;

a second source/drain region in the semiconductor substrate;

an inter-layer dielectric over the first source/drain region and the second source/drain region;

a first source/drain contact extending through the inter-layer dielectric, the first source/drain contact connected to the first source/drain region;

a first contact spacer surrounding the first source/drain contact;

a first void disposed between the first contact spacer and the inter-layer dielectric;

a second source/drain contact extending through the inter-layer dielectric, the second source/drain contact connected to the second source/drain region;

a second contact spacer surrounding the second source/drain contact, the second contact spacer and the first contact spacer having a same width; and

a second void disposed between the second contact spacer and the inter-layer dielectric, the second void having a greater width than the first void.

13. The device of claim 12 further comprising:

a first spacer disposed between the first contact spacer and the inter-layer dielectric, the first void disposed over the first spacer, the first spacer and the first void having a same width; and

a second spacer disposed between the second contact spacer and the inter-layer dielectric, the second void disposed over the second spacer, the second spacer and the second void having a same width.

14. The device of claim 13 , wherein the first spacer has a greater height than the second spacer.

15. The device of claim 13 , wherein the first spacer and the second spacer have a greater etch rate than the first contact spacer and the second contact spacer relative an etching process.

16. The device of claim 12 further comprising:

a first spacer disposed between the first contact spacer and the inter-layer dielectric, the first void disposed over the first spacer, the first spacer and the first void having a same width, wherein a top surface of the second source/drain region is exposed to the second void.

17. The device of claim 16 , wherein the first spacer has a greater etch rate than the first contact spacer and the second contact spacer relative an etching process.

18. The device of claim 12 , wherein a top surface of the first source/drain region is exposed to the first void, and a top surface of the second source/drain region is exposed to the second void.

19. The device of claim 12 further comprising:

a first dielectric layer having a first portion, a second portion, and a third portion, the first portion disposed between the first contact spacer and the inter-layer dielectric, the second portion disposed between the second contact spacer and the inter-layer dielectric, the third portion disposed over the first portion and the second portion.

20. The device of claim 19 , wherein the second portion of the first dielectric layer has a greater height than the first portion of the first dielectric layer.