Semiconductor devices
In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.
1. A device comprising:
a first source/drain region in a substrate;
a second source/drain region in the substrate;
a first inter-layer dielectric over the first source/drain region and the second source/drain region;
a first source/drain contact extending through the first inter-layer dielectric, the first source/drain contact connected to the first source/drain region, the first source/drain contact having a first width;
a first void between the first source/drain contact and first sidewalls of the first inter-layer dielectric, the first sidewalls of the first inter-layer dielectric separated by a first distance;
a second source/drain contact extending through the first inter-layer dielectric, the second source/drain contact connected to the second source/drain region, the second source/drain contact having a second width, the second width less than the first width; and
a second void between the second source/drain contact and second sidewalls of the first inter-layer dielectric, the second sidewalls of the first inter-layer dielectric separated by a second distance,
wherein a first difference between the first distance and the first width is greater than a second difference between the second distance and the second width.
2. The device of claim 1 , wherein the first void has a greater width than the second void.
3. The device of claim 1 , further comprising:
a first spacer between the first source/drain contact and the first inter-layer dielectric, the first void disposed over the first spacer; and
a second spacer between the second source/drain contact and the first inter-layer dielectric, the second void disposed over the second spacer.
4. The device of claim 3 , wherein a first height of the first spacer is different from a second height of the second spacer.
5. The device of claim 3 , further comprising:
a second inter-layer dielectric over the first inter-layer dielectric, the first source/drain contact and the second source/drain contact extending through the second inter-layer dielectric,
wherein the first spacer and the second spacer each comprise a first material, the second inter-layer dielectric comprises a second material, and the first material has a faster etch rate than the second material relative a reaction gas.
6. The device of claim 5 , wherein a bottom surface of the second inter-layer dielectric is exposed to the first void and to the second void.
7. A device comprising:
a first source/drain region in a semiconductor substrate;
a second source/drain region in the semiconductor substrate;
an inter-layer dielectric over the first source/drain region and the second source/drain region;
a first source/drain contact extending through the inter-layer dielectric, the first source/drain contact connected to the first source/drain region;
a first void between the first source/drain contact and the inter-layer dielectric;
a second source/drain contact extending through the inter-layer dielectric, the second source/drain contact connected to the second source/drain region; and
a second void between the second source/drain contact and the inter-layer dielectric, the second void having a greater width than the first void.
8. The device of claim 7 , further comprising:
a first spacer contacting a top surface of the first source/drain region, the first void disposed over the first spacer.
9. The device of claim 8 , wherein a first material of the first spacer has a greater etch rate than a second material of the inter-layer dielectric relative an etching process.
10. The device of claim 9 , wherein the first material is undoped silicon and the second material is silicon oxide.
11. The device of claim 8 , further comprising:
a second spacer contacting a top surface of the second source/drain region, the second void disposed over the second spacer.
12. The device of claim 8 , wherein a top surface of the second source/drain region is exposed to the second void.
13. The device of claim 7 , wherein a top surface of the first source/drain region is exposed to the first void, and a top surface of the second source/drain region is exposed to the second void.
14. The device of claim 7 , further comprising:
a first dielectric layer having a first portion, a second portion, and a third portion, the first portion disposed between the first source/drain contact and the inter-layer dielectric, the second portion disposed between the second source/drain contact and the inter-layer dielectric, the third portion disposed over the first portion and the second portion.
15. The device of claim 14 , wherein the second portion of the first dielectric layer has a greater height than the first portion of the first dielectric layer.
16. A device comprising:
a gate electrode;
a source/drain region adjacent the gate electrode;
a first inter-layer dielectric over the source/drain region;
a second inter-layer dielectric over the first inter-layer dielectric;
a source/drain contact extending through the first inter-layer dielectric and the second inter-layer dielectric, the source/drain contact connected to the source/drain region; and
a void between the source/drain contact and the first inter-layer dielectric, a bottom surface of the second inter-layer dielectric being exposed to the void.
17. The device of claim 16 , further comprising:
a first spacer between the source/drain contact and the first inter-layer dielectric, the first spacer disposed over the source/drain region, the void disposed over the first spacer.
18. The device of claim 17 , wherein a first distance between a top surface of the source/drain region and a top surface of the first spacer is less than a second distance between the top surface of the first spacer and a top surface of the gate electrode.
19. The device of claim 16 , further comprising:
a first dielectric layer having a first portion and a second portion, the first portion disposed over the second inter-layer dielectric and the source/drain contact, the second portion disposed between the source/drain contact and the second inter-layer dielectric.
20. The device of claim 16 , wherein the second inter-layer dielectric comprises an impurity, the impurity comprising Ge, B, Ar, Sn, or Si.