Full air-gap spacers for gate-all-around nanosheet field effect transistors
Semiconductor devices include a stack of vertically arranged channel layers. A gate stack is formed above, between, and around the vertically arranged channel layers. Source and drain regions and source and drain conductive contacts are formed. Inner spacers are formed between the vertically arranged channel layers, each having an inner air gap and a recessed layer formed from a first dielectric material. Outer spacers are formed between the gate stack and the source and drain conductive contacts, each having a second dielectric material that is pinched off to form an outer air gap.
1. A semiconductor device, comprising:
a stack of vertically arranged channel layers;
a gate stack formed above, between, and around the vertically arranged channel layers;
source and drain regions;
source and drain conductive contacts;
inner spacers between the vertically arranged channel layers, each comprising an inner air gap and a recessed layer formed from a first dielectric material, wherein the inner air gaps expose horizontal surfaces of edges of the vertically arranged channel layers; and
outer spacers between the gate stack and the source and drain conductive contacts, each comprising a second dielectric material that is pinched off to form an outer air gap.
2. The semiconductor device of claim 1 , wherein the first dielectric material is silicon nitride and the second dielectric material is silicoboron carbonitride.
3. The semiconductor device of claim 1 , wherein the recessed layers conform to surfaces of adjacent channel layers and of the gate stack and do not extend to respective side edges of the channel layers.
4. The semiconductor device of claim 1 , wherein the recessed layers have a thickness between about 1 nm and about 2 nm.
5. The semiconductor device of claim 1 , wherein the source and drain regions are grown from sidewalls of the vertically arranged channel layers.
6. The semiconductor device of claim 1 , wherein each recessed layer includes a dielectric layer that contacts the gate stack and that is recessed relative to sidewalls of the vertically arranged channel layers.
7. The semiconductor device of claim 6 , wherein each recessed layer is formed conformally on surfaces of the gate stack and the vertically arranged channel layers, such that each inner air gap includes a portion that is within a boundary established by a lateral extension of the recessed layer and a portion that is outside of the boundary established by the lateral extension of the recessed layer.
8. The semiconductor of claim 1 , wherein the second dielectric material does not extend between the vertically arranged channel layers.
9. The semiconductor device of claim 1 , wherein the second dielectric material is formed conformally on sides of the source and drain conductive contacts.
10. A semiconductor device, comprising:
a stack of vertically arranged channel layers;
a gate stack formed above, between, and around the vertically arranged channel layers;
source and drain regions grown from sidewalls of the vertically arranged channel layers;
source and drain conductive contacts;
inner spacers between the vertically arranged channel layers, each comprising an inner air gap and a recessed layer formed from a first dielectric material, wherein each recessed layer contacts the gate stack and is recessed relative to sidewalls of the vertically arranged channel layers, wherein the inner air gaps expose horizontal surfaces of edges of the vertically arranged channel layers; and
outer spacers between the gate stack and the source and drain conductive contacts, each comprising a second dielectric material that is pinched off to form an outer air gap.
11. The semiconductor device of claim 10 , wherein the first dielectric material is silicon nitride and the second dielectric material is silicoboron carbonitride.
12. The semiconductor device of claim 10 , wherein the recessed layers conform to surfaces of adjacent channel layers and of the gate stack and do not extend to respective side edges of the channel layers.
13. The semiconductor device of claim 10 , wherein the recessed layers have a thickness between about 1 nm and about 2 nm.
14. The semiconductor device of claim 10 , wherein each recessed layer is formed conformally on surfaces of the gate stack and the vertically arranged channel layers, such that each inner air gap includes a portion that is within a boundary established by a lateral extension of the recessed layer and a portion that is outside of the boundary established by the lateral extension of the recessed layer.
15. The semiconductor of claim 10 , wherein the second dielectric material does not extend between the vertically arranged channel layers.
16. The semiconductor device of claim 10 , wherein the second dielectric material is formed conformally on sides of the source and drain conductive contacts.
17. A semiconductor device, comprising:
a stack of vertically arranged channel layers;
a gate stack formed above, between, and around the vertically arranged channel layers;
source and drain regions grown from sidewalls of the vertically arranged channel layers;
source and drain conductive contacts;
inner spacers between the vertically arranged channel layers, each comprising an inner air gap and a recessed layer formed from silicon nitride, wherein each recessed layer is formed conformally on surfaces of the gate stack and the vertically arranged channel layers and is recessed relative to sidewalls of the vertically arranged channel layers, wherein the inner air gaps expose horizontal surfaces of edges of the vertically arranged channel layers; and
outer spacers between the gate stack and the source and drain conductive contacts, each comprising a silicoboron carbonitride layer that is formed conformally on sides of the source and drain conductive contacts and is pinched off to form an outer air gap.
18. The semiconductor device of claim 17 , wherein the recessed layers conform to surfaces of adjacent channel layers and of the gate stack and do not extend to respective side edges of the channel layers.
19. The semiconductor device of claim 17 , wherein the recessed layers have a thickness between about 1 nm and about 2 nm.
20. The semiconductor device of claim 17 , wherein the inner air gap includes a portion that is within a boundary established by a lateral extension of the recessed layer and a portion that is outside of the boundary established by the lateral extension of the recessed layer.