Formation of a partial air-gap spacer
A method is presented for reducing parasitic capacitance. The method includes forming multi-layer spacers between source/drain regions, forming a dielectric liner over the multi-layer spacers and the source/drain regions, forming gate structures adjacent the multi-layer spacers, forming a self-aligned contact cap over the gate structures, and removing a sacrificial layer of each of the multi-layer spacers to form air-gaps between the gate structures and the source/drain regions.
1. A method for reducing parasitic capacitance, the method comprising:
forming a three-layer spacer in direct contact with sidewalls of a sacrificial layer;
forming a source/drain region within a substrate;
forming a dielectric liner over the sacrificial layer and the source/drain region;
forming an inter-layer dielectric (ILD) over the source/drain region;
replacing the sacrificial layer with a gate structure;
replacing the ILD with a conducting material directly contacting a top surface of the source/drain region and directly contacting sidewalls of the three-layer spacer; and
removing a middle layer of the three-layer spacer to form air-gaps between the gate structure and the source/drain region.
2. The method of claim 1 , wherein the first and third layers of the three-layer spacer are silicon boron carbon nitride (SiBCN) layers, and the middle layer of the three-layer spacer is a germanium dioxide (GeO 2 ) layer.
3. The method of claim 2 , wherein the GeO 2 layer is nitrized to form a germanium oxynitride (GeON) cap thereon.
4. The method of claim 3 , wherein the three-layer spacer has a total thickness of about 6 nm.
5. The method of claim 4 , further comprising forming a self-aligned contact cap over the gate structure before replacing the ILD with the conducting material.
6. The method of claim 5 , further comprising partially recessing the self-aligned contact cap after replacing the ILD with the conducting material.
7. The method of claim 6 , wherein the recessing of the self-aligned contact cap results in removal of the GeON cap formed over the GeO 2 layer before forming the air-gaps.
8. The method of claim 1 , wherein each of the air-gaps extends a length of the gate structure.
9. The method of claim 1 , wherein each of the air-gaps extends to a sidewall of the source/drain region.
10. A method for reducing parasitic capacitance, the method comprising:
forming multi-layer spacers between source/drain regions;
forming a dielectric liner over the multi-layer spacers and the source/drain regions;
forming gate structures adjacent the multi-layer spacers;
depositing a conducting material in direct contact with the source/drain regions and in direct contact with sidewalls of the multi-layer spacers;
forming a self-aligned contact cap over the gate structures; and
removing a sacrificial layer of each of the multi-layer spacers to form air-gaps between the gate structures and the source/drain regions, the air-gaps having a substantially L-shaped configuration.
11. The method of claim 10 , wherein the sacrificial layer of the multi-layer spacers is a germanium dioxide (GeO 2 ) layer.
12. The method of claim 11 , wherein the GeO 2 layer is nitrized to form a germanium oxynitride (GeON) cap thereon.
13. The method of claim 12 , wherein the self-aligned contact cap is partially recessed to remove the GeON cap formed over the GeO 2 layer before forming the air-gaps.
14. The method of claim 10 , wherein each of the air-gaps extends a length of the gate structures.
15. The method of claim 10 , wherein each of the air-gaps extends to a sidewall of the source/drain regions.