Semiconductor device and method of fabricating the same

1. A method of fabricating a semiconductor device, comprising:

forming a gate structure on a fin, wherein the gate structure includes a first gate spacer, a second gate spacer, and a gate electrode interposed therebetween;

forming a source/drain contact on the fin;

forming a source/drain electrode on the source/drain contact;

forming an air pocket pattern on the source/drain contact, wherein the air pocket pattern includes a first low-k dielectric pattern and an energy removable pattern between the gate structure and the source/drain electrode; and

forming an air gap defined in part by the first low-k dielectric pattern by applying energy to the energy removable pattern,

wherein the forming of the source/drain electrode includes:

forming an interlayer dielectric layer covering the gate structure and the fin;

forming a trench exposing a part of the fin;

forming a source/drain region in the part of the fin through the trench;

forming the source/drain contact on the source/drain region, and

wherein the forming of the source/drain contact includes:

forming a metal layer within the trench;

forming a nitride layer on the metal layer;

forming an etch mask covering a bottom portion of the nitride layer; and

removing partially the metal layer and the nitride layer exposed by the etch mask to form a patterned metal layer and a patterned nitride layer.

2. The method of claim 1 ,

wherein the forming of the air gap includes separating the energy removable pattern into a top sealing and a bottom sealing,

wherein the bottom sealing is in contact with the source/drain contact, and

wherein the air gap is interposed between the bottom sealing and the top sealing.

3. The method of claim 1 ,

wherein the forming of the source/drain contact further includes a silicidation process, and wherein the silicidation process is performed by the applying of the energy to the energy removable pattern.

4. The method of claim 1 ,

wherein the forming of the air pocket pattern is before the forming of the source/drain electrode, and

wherein the applying of the energy to the energy removable pattern is performed after the forming of the source/drain electrode.

5. The method of claim 1 ,

wherein the air pocket pattern further includes a second low-k dielectric pattern, and

wherein the energy removable pattern is interposed between the first low-k dielectric pattern and the second low-k dielectric pattern.

6. The method of claim 1 , further comprising:

forming a nitride liner between the air pocket pattern and the source/drain electrode.

7. The method of claim 6 ,

wherein the air pocket pattern further includes a second low-k dielectric pattern,

wherein the energy removable pattern is interposed between the first low-k dielectric pattern and the second low-k dielectric pattern, and

wherein the second low-k dielectric pattern is interposed between the energy removable pattern and the nitride liner,

wherein the first low-k dielectric pattern is in contact with the second gate spacer,

wherein the second low-k dielectric pattern is in contact with the nitride liner, and

wherein the first low-k dielectric pattern and the second low-k dielectric pattern are in contact with the source/drain contact.

8. The method of claim 1 ,

wherein the forming of the source/drain contact further includes:

performing a silicidation process on the patterned metal layer.

9. The method of claim 8 ,

wherein the silicidation process and the forming of the air gap are performed at the same time.

10. The method of claim 1 ,

wherein the forming of the etch mask includes:

forming an organic dielectric layer to fill the trench; and

performing an etch-back process on the organic dielectric layer to form the etch mask.

11. A method of forming a trench silicide contact, the method comprising:

perforating one or more layers to create a perforation exposing at least a portion of a silicon substrate;

depositing a first material through the perforation, the first material including a first metal that is reactive with silicon;

annealing the silicon substrate to form a silicide in the exposed portion of the silicon substrate;

removing the first material from sidewalls of the layers;

depositing a liner material onto the sidewalls of the layers, the liner material having a lower dielectric constant than that of silicon dioxide and including an energy removal porous material;

depositing a second material through the perforation, the deposited second material being in electrical contact with the silicide;

forming an etch mask covering a bottom portion of the deposited second material; and

removing partially the liner material and the deposited second material exposed by the etch mask to form a patterned layer of the first material and a patterned layer of the liner material.