Air spacers around contact plugs and method forming same
A method includes forming an opening in a first dielectric layer. A region underlying the first dielectric layer is exposed to the opening. The method further includes depositing a dummy silicon layer extending into the opening, and depositing an isolation layer. The isolation layer and the dummy layer include a dummy silicon ring and an isolation ring, respectively, in the opening. The opening is filled with a metallic region, and the metal region is encircled by the isolation ring. The dummy silicon layer is etched to form an air spacer. A second dielectric layer is formed to seal the air spacer.
1. A device comprising:
a transistor comprising:
a semiconductor region;
a gate stack on the semiconductor region;
a source/drain region aside of the gate stack; and
a silicide region over the source/drain region;
a first inter-layer dielectric over the source/drain region, wherein the gate stack is in the first inter-layer dielectric;
a contact plug electrically connecting to the transistor, wherein the contact plug comprises a part in the first inter-layer dielectric; and
an air spacer comprising a first portion in the first inter-layer dielectric, and a second portion higher than the first inter-layer dielectric.
2. The device of claim 1 further comprising a second inter-layer dielectric over the first inter-layer dielectric, wherein the second portion of the air spacer is in the second inter-layer dielectric.
3. The device of claim 1 , wherein the first inter-layer dielectric is exposed to the air spacer.
4. The device of claim 3 further comprising a contact etch stop layer under the first inter-layer dielectric, wherein an edge of the contact etch stop layer is further exposed to the air spacer.
5. The device of claim 4 , wherein the source/drain region comprises a top surface contacting a bottom surface of the contact etch stop layer, and wherein the air spacer extends into the source/drain region.
6. The device of claim 1 further comprising:
a silicon layer, wherein a sidewall of the silicon layer is exposed to the air spacer, and wherein the source/drain region is formed of a material different from the silicon layer.
7. The device of claim 6 , wherein the silicon layer is an amorphous silicon layer.
8. The device of claim 6 , wherein the silicon layer is a polysilicon layer.
9. The device of claim 1 further comprising a dielectric isolation layer encircled by, and exposed to, the air spacer.
10. The device of claim 9 , wherein the air spacer comprises a portion directly under the dielectric isolation layer.
11. A device comprising:
a gate stack;
a source/drain region on a side of the gate stack;
a silicide region over the source/drain region;
a first inter-layer dielectric over the silicide region;
a contact plug over the silicide region and in the first inter-layer dielectric;
an etch stop layer over the first inter-layer dielectric; and
an air spacer, wherein the air spacer forms a full ring encircling the contact plug, and wherein the air spacer comprises:
a first portion in the first inter-layer dielectric; and
a second portion in the etch stop layer.
12. The device of claim 11 further comprising a dielectric isolation layer forming a ring encircling the contact plug, wherein the dielectric isolation layer is further encircled by the air spacer.
13. The device of claim 12 , wherein the air spacer comprises a lower portion overlapped by the dielectric isolation layer.
14. The device of claim 11 , wherein a top surface of the source/drain region is exposed to the air spacer.
15. The device of claim 11 further comprising a second inter-layer dielectric over the etch stop layer, wherein the air spacer further comprises a third portion in the second inter-layer dielectric.
16. The device of claim 11 , wherein the first inter-layer dielectric is exposed to the air spacer.
17. The device of claim 11 , wherein in a cross-sectional view of the device, a first bottommost end of the air spacer is lower than a second bottommost end of the first inter-layer dielectric.
18. A device comprising:
a bulk semiconductor substrate;
a semiconductor fin higher than a top surface of the bulk semiconductor substrate;
a gate stack on the semiconductor fin;
a gate spacer on a first sidewall of the gate stack;
a dielectric region on a second sidewall of the gate spacer, wherein the dielectric region and the gate stack are on opposing sides of the gate spacer;
a dielectric isolation layer encircled by the dielectric region;
an air spacer between the dielectric region and the dielectric isolation layer, wherein a portion of the air spacer is higher than a topmost end of the gate spacer; and
a source/drain region exposed to the air spacer.
19. The device of claim 18 , wherein both of the dielectric region and the dielectric isolation layer are exposed to the air spacer.
20. The device of claim 18 , wherein the air spacer forms a ring encircling the dielectric isolation layer.