Metal gates of transistors having reduced resistivity

1. A method comprising:

forming a transistor comprising:

forming a gate dielectric on a semiconductor region;

forming a gate electrode over the gate dielectric; and

forming a source/drain region extending into the semiconductor region;

forming a hard mask over and contacting the gate electrode;

forming a source/drain contact plug over and electrically coupling to the source/drain region; and

forming a gate contact plug over and in contact with the gate electrode, wherein the forming the gate contact plug comprises:

removing the hard mask to form an opening;

depositing a metal silicide layer extending into the opening; and

performing a planarization process to remove excess portions of the metal silicide layer.

2. The method of claim 1 further comprising, before the metal silicide layer is deposited, depositing a metal nitride barrier layer extending into the opening.

3. The method of claim 1 , wherein the depositing the metal silicide layer comprises depositing a cobalt silicide layer.

4. The method of claim 1 , wherein the forming the gate contact plug further comprises depositing a cobalt layer over the metal silicide layer.

5. The method of claim 4 , wherein the depositing the metal silicide layer comprises:

depositing a first sub metal silicide layer at a first temperature; and

depositing a second sub metal silicide layer at a second temperature lower than the first temperature.

6. The method of claim 5 , wherein upper portions of the metal silicide layer have increasingly lower silicon atomic percentages than respective lower portions of the metal silicide layer.

7. The method of claim 5 , wherein a top portion of the metal silicide layer is substantially free from silicon.

8. The method of claim 1 , wherein a metal silicide is deposited directly to form the metal silicide layer, and the metal silicide layer is formed without a siliciding process.

9. The method of claim 1 , wherein the forming the gate electrode comprises:

depositing a titanium nitride containing layer;

depositing a work function layer over the titanium nitride containing layer, wherein the titanium nitride containing layer is over the work function layer; and

performing an additional planarization process to remove excess portions of the titanium nitride containing layer and the work function layer.

10. The method of claim 1 further comprising:

forming a source/drain silicide over and contacting the source/drain region, wherein the forming the source/drain contact plug further comprises depositing an additional metal silicide layer.

11. A method comprising:

forming a source/drain region;

forming a trench between gate spacers and adjacent to the source/drain region;

forming a replacement gate dielectric extending into the trench;

forming a replacement gate electrode over the replacement gate dielectric;

forming a gate contact plug over and electrically coupling to the replacement gate electrode; and

forming a source/drain contact plug over the source/drain region, wherein at least one of the forming the gate contact plug and the forming the source/drain contact plug comprises:

depositing a barrier layer;

depositing a metal silicide layer over the barrier layer; and

performing a planarization process to remove excess portions of the barrier layer and the metal silicide layer.

12. The method of claim 11 , wherein the forming the gate contact plug comprises the depositing the barrier layer and the depositing the metal silicide layer.

13. The method of claim 11 , wherein the forming the source/drain contact plug comprises the depositing the barrier layer and the depositing the metal silicide layer.

14. The method of claim 11 , wherein the at least one of the forming the gate contact plug and the forming the source/drain contact plug further comprises depositing a cobalt layer over and contacting the metal silicide layer.

15. The method of claim 11 , wherein the metal silicide layer is deposited as having a plurality of sub-layers having different percentages of silicon.

16. The method of claim 15 , wherein the plurality of sub-layers are deposited by adjusting temperatures to result in the different percentages of silicon.

17. A method comprising:

forming a gate stack between gate spacers;

forming a gate contact plug over and contacting the gate stack;

forming a source/drain region adjacent to the gate stack;

performing a silicidation process to form a first silicide layer over and contacting the source/drain region;

forming a source/drain contact plug over and joined to the first silicide layer, wherein a contact-formation process selected from the forming the source/drain contact plug and the forming the gate contact plug comprises:

depositing a first metal silicide layer; and

depositing a second metal silicide layer over the first metal silicide layer, wherein the second metal silicide layer has a lower silicon atomic percentage than the first metal silicide layer.

18. The method of claim 17 , wherein the contact-formation process further comprises depositing a barrier layer, and wherein the first metal silicide layer is formed over and contacting the barrier layer.

19. The method of claim 17 , wherein the contact-formation process further comprises:

depositing a cobalt layer over the second metal silicide layer, wherein the cobalt layer is substantially free from silicon.

20. The method of claim 17 , wherein an entirety of a metal contact formed by the contact-formation process is metal-silicide comprising.